低密度校驗碼（LDPC，Low Density Parity Check Code）是一種性能接近香農極限的信道編碼，已被廣泛地采用到各種無線通信領域標準中，包括我國的數字電視地面傳輸標準、歐洲第二代衛星數字視頻廣播標準（DVB-S2，Digital Video Broadcasting-Satellite 2）、IEEE 802.11n、IEEE 802.16e等。它是3G乃至將來4G通信系統中的核心技術之一。 當今LDPC碼構造的主流方向有兩個，分別是結合準循環（QC，Quasi Cyclic）移位結構的單次擴展構造和類似重復累積（RA，Repeat Accumulate）碼構造。相應地，主要的LDPC碼編碼算法有基于生成矩陣的算法和基于迭代譯碼的算法。基于生成矩陣的編碼算法吞吐量高，但是需要較多的寄存器和ROM資源；基于迭代譯碼的編碼算法實現簡單，但是吞吐量不高，且不容易構造高性能的好碼。 本文在研究了上述幾種碼構造和編碼算法之后，結合編譯碼器綜合實現的復雜度考慮，提出了一種切實可行的基于二次擴展（Dex，duplex Expansion）的QC-LDPC碼構造方法，以實現高吞吐量的LDPC碼收發端；并且充分利用該類碼校驗矩陣準循環移位結構的特點，結合RU算法，提出了一種新編碼器的設計方案。 基于二次擴展的QC-LDPC碼構造方法，是通過對母矩陣先后進行亂序擴展（Pex，Permutation Expansion）和循環移位擴展（CSEx，Cyclic Shift Expansion）實現的。在此基礎上，為了實現可變碼長、可變碼率，一般編譯碼器需同時支持多個亂序擴展和循環移位擴展的擴展因子。本文所述二次擴展構造方法的特點在于，固定循環移位擴展的擴展因子大小不變，支持多個亂序擴展的擴展因子，使得譯碼器結構得以精簡；構造得到的碼字具有近似規則碼的結構，便于硬件實現；（偽）隨機生成的循環移位系數能夠提高碼字的誤碼性能，是對硬件實現和誤碼性能的一種折中。 新編碼器在很大程度上考慮了資源的復用，使得實現復雜度近似與碼長成正比。考慮到吞吐量的要求，新編碼器結構完全拋棄了RU算法中串行的前向替換（FS，Forward Substitution）模塊，同時簡化了流水線結構，由原先RU算法的6級降低為4級；為了縮短編碼延時，設計時安排每一級流水線計算所需的時鐘數大致相同。 這種碼字構造和編碼聯合設計方案具有以下優勢：相比RU算法，新方案對可變碼長、可變碼率的支持更靈活，吞吐量也更大；相比基于生成矩陣的編碼算法，新方案節省了50％以上的寄存器和ROM資源，單位資源下的吞吐量更大；相比類似重復累積碼結構的基于迭代譯碼的編碼算法，新方案使高性能LDPC碼的構造更為方便。以上結果都在Xilinx Virtex II pro 70 FPGA上得到驗證。 通過在實驗板上實測表明，上述基于二次擴展的QC-LDPC碼構造和相應的編碼方案能夠實現高吞吐量LDPC碼收發端，在實際應用中具有很高的價值。 目前，LDPC碼正向著非規則、自適應、信源信道及調制聯合編碼方向發展。跨層聯合編碼的構造方法，及其對應的編碼算法，也必將成為信道編碼理論未來的研究重點。
上傳時間： 2013-07-26
上傳用戶：qoovoop
介紹一種簡單射頻識別系統設計。該設計包括閱讀器、應答器和線圈3部分。由單片機控制閱讀器向應答器發射無線信號，并接收應答器回送的信號，再通過分析回送信號識別物品。閱讀器和應答器之間以半雙工通信方式通信。 Abstract: A simple design of radio frequency identification system is given in this paper.The design includes reader,responder and winding.Through MCU，signals are sent to responder from reader，then corresponding signals are sent back. According to the analysis of the signals sent back，the objects can be identified.Half-duplex communication is adopted? between? reader? and? responder.
上傳時間： 2013-10-11
上傳用戶：plsee
基于幅移鍵控技術ASK（Amplitude-Shift Keying），以C8051F340單片機作為監測終端控制器，C8051F330D單片機作為探測節點控制器，采用半雙工的通信方式，通過監控終端和探測節點的無線收發電路，實現數據的雙向無線傳輸。收發電路采用直徑為0.8 mm的漆包線自行繞制成圓形空心線圈天線，天線直徑為（3.4±0.3）cm。試驗表明，探測節點與監測終端的通信距離為24 cm，通過橋接方式，節點收發功率為102 mW時，節點間的通信距離可達20 cm。與傳統無線收發模塊相比，該無線收發電路在受體積、功耗、成本限制的場合有廣闊的應用前景。 Abstract: Based on ASK technology and with the C8051F340 and C8051F330D MCU as the controller， using half-duplex communication mode， this paper achieves bi-directional data transfer. Transceiver circuit constituted by enameled wire which diameter is 0.8mm and wound into a diameter （3.4±0.3） cm circular hollow coil antenna. Tests show that the communication distance between detection and monitoring of the terminal is 24cm，the distance is up to 20cm between two nodes when using the manner of bridging and the node transceiver power is 102mW. Compared with the conventional wireless transceiver modules， the circuit has wide application prospect in small size， low cost and low power consumption and other characteristics.
上傳時間： 2013-10-19
上傳用戶：xz85592677
The LPC1700 Ethernet block contains a full featured 10 Mbps or 100 Mbps Ethernet MAC (Media Access Controller) designed to provide optimized performance through the use of DMA hardware acceleration. Features include a generous suite of control registers, half or full duplex operation, flow control, control frames, hardware acceleration for transmit retry, receive packet filtering and wake-up on LAN activity. Automatic frame transmission and reception with Scatter-Gather DMA off-loads many operations from the CPU.
上傳時間： 2013-11-09
上傳用戶：geshaowei
The C500 microcontroller family usually provides only one on-chip synchronous serialchannel (SSC). If a second SSC is required, an emulation of the missing interface mayhelp to avoid an external hardware solution with additional electronic components.The solution presented in this paper and in the attached source files emulates the mostimportant SSC functions by using optimized SW routines with a performance up to 25KBaud in Slave Mode with half duplex transmission and an overhead less than 60% atSAB C513 with 12 MHz. Due to the implementation in C this performance is not the limitof the chip. A pure implementation in assembler will result in a strong reduction of theCPU load and therefore increase the maximum speed of the interface. In addition,microcontrollers like the SAB C505 will speed up the interface by a factor of two becauseof an optimized architecture compared with the SAB C513.Moreover, this solution lays stress on using as few on-chip hardware resources aspossible. A more excessive consumption of those resources will result in a highermaximum speed of the emulated interface.Due to the restricted performance of an 8 bit microcontroller a pin compatible solution isprovided only; the internal register based programming interface is replaced by a set ofsubroutine calls.The attached source files also contain a test shell, which demonstrates how to exchangeinformation between an on-chip HW-SSC and the emulated SW-SSC via 5 external wiresin different operation modes. It is based on the SAB C513 (Siemens 8 bit microcontroller).A table with load measurements is presented to give an indication for the fraction of CPUperformance required by software for emulating the SSC.
標簽： synchronous Emulating serial
上傳時間： 2014-01-31
上傳用戶：z1191176801
8051參考設計，與其他8051的免費IP相比，文檔相對較全，Oregano System 提供 This is version 1.3 of the MC8051 IP core. September 2002: Oregano Systems - Design & Consulting GesmbH Change history: - Improved tb_mc8051_siu_sim.vhd to verify duplex operation. - Corrected problem with duplex operation in file mc8051_siu_rtl.vhd
上傳時間： 2014-12-28
上傳用戶：tb_6877751
AFDX（ Avionics Full duplex Switch Ethernet）是空客公司首先提出的， 在商用以太網技術的基礎上，通過增加特殊功能來保證航空應用的確定性和可靠性，是目前最先進的機載通信網絡。文中針對航電設備與總線網絡通信出現的故障，設計了某型號飛機AFDX總線監控器，該設備是一個便攜式工控機，通過擴展AFDX總線接口卡，實時、高速、可靠的對總線上的數據進行記錄、分析、顯示，并依照航電總線標準ICD（接口控制文件）庫進行解析，快速準確的定位故障，避免設備的無故障拆裝，提高維護效率。仿真實驗表明：該監控器可實時監控航電AFDX 總線上的所有動態信息，對信息的分析處理正確，能滿足設計需求。
上傳時間： 2013-10-17
上傳用戶：zyt
8051參考設計，與其他8051的免費IP相比，文檔相對較全，Oregano System 提供 This is version 1.3 of the MC8051 IP core. September 2002: Oregano Systems - Design & Consulting GesmbH Change history: - Improved tb_mc8051_siu_sim.vhd to verify duplex operation. - Corrected problem with duplex operation in file mc8051_siu_rtl.vhd
上傳時間： 2013-11-06
上傳用戶：XLHrest
Features • Compatible with MCS-51® Products • 8K Bytes of In-System Programmable (ISP) Flash Memory – Endurance: 1000 Write/Erase Cycles • 4.0V to 5.5V Operating Range • Fully Static Operation: 0 Hz to 33 MHz • Three-level Program Memory Lock • 256 x 8-bit Internal RAM • 32 Programmable I/O Lines • Three 16-bit Timer/Counters • Eight Interrupt Sources • Full duplex UART Serial Channel • Low-power Idle and Power-down Modes • Interrupt Recovery from Power-down Mode • Watchdog Timer • Dual Data Pointer • Power-off Flag
標簽： 8226 Programmable Compatible In-System
上傳時間： 2015-06-27
上傳用戶：dianxin61
看n2實例 #Create a simulator object set ns [new Simulator] #Define different colors for data flows #$ns color 1 Blue #$ns color 2 Red #Open the nam trace file set nf [open out-1.nam w] $ns namtrace-all $nf set f0 [open out0.tr w] set f1 [open out1.tr w] #Define a finish procedure proc finish {} { global ns nf $ns flush-trace #Close the trace file close $nf #Execute nam on the trace file exit 0 } #Create four nodes set n0 [$ns node] set n1 [$ns node] set n2 [$ns node] set n3 [$ns node] #Create links between the nodes $ns duplex-link $n0 $n2 1Mb 10ms
標簽： simulator Simulator different Create
上傳時間： 2016-07-02
上傳用戶：wfl_yy
