高的工作電壓高達100V N雙N溝道MOSFET同步驅動 The D810DCDC is a synchronous step-down switching regulator controller that can directly step-down voltages from up to 100V, making it ideal for telecom and automotive applications. The D810DCDC uses a constant on-time valley current control architecture to deliver very low duty cycles with accurate cycle-by-cycle current limit, without requiring a sense resistor. A precise internal reference provides 0.5% DC accuracy. A high bandwidth (25MHz) error amplifi er provides very fast line and load transient response. Large 1Ω gate drivers allow the D810DCDC to drive multiple MOSFETs for higher current applications. The operating frequency is selected by an external resistor and is compensated for variations in VIN and can also be synchronized to an external clock for switching-noise sensitive applications. Integrated bias control generates gate drive power from the input supply during start-up and when an output shortcircuit occurs, with the addition of a small external SOT23 MOSFET. When in regulation, power is derived from the output for higher effi ciency.
Automotive batteries, industrial power supplies, distributedsupplies and wall transformers are all sources ofwide-ranging high voltage inputs. The easiest way to stepdown these sources is with a high voltage monolithicstep-down regulator that can directly accept a wide inputrange and produce a well-regulated output. The LT®3493accepts inputs from 3.6V to 36V and LT3481 acceptsinputs from 3.6V to 34V. Both provide excellent lineand load regulation and dynamic response. The LT3481offers a high effi ciency solution over a wide load range andkeeps the output ripple low during Burst Mode® operationwhile the LT3493 provides a tiny solution with minimalexternal components. The LT3493 operates at 750kHzand the LT3481 has adjustable frequency from 300kHzto 2.8MHz. High frequency operation enables the use ofsmall, low cost inductors and ceramic capacitors.
In a recent discussion with a system designer, the requirementfor his power supply was to regulate 1.5Vand deliver up to 40A of current to a load that consistedof four FPGAs. This is up to 60W of power that must bedelivered in a small area with the lowest height profi lepossible to allow a steady fl ow of air for cooling. Thepower supply had to be surface mountable and operateat high enough effi ciency to minimize heat dissipation.He also demanded the simplest possible solution so histime could be dedicated to the more complex tasks. Asidefrom precise electrical performance, this solution had toremovethe heat generated during DC to DC conversionquickly so that the circuit and the ICs in the vicinity do notoverheat. Such a solution requires an innovative designto meet these criteria:
The MAX9257/MAX9258 programmable serializer/deserializer (SerDes) devices transfer both video data and control signals over the same twisted-pair cable. However, control data can only be transmitted during the vertical blank time, which is indicated by the control-channel-enabled output (CCEN) signal. The electronic control unit (ECU) firmware designer needs to know how quickly to respond to the CCEN signal before it times out and how to calculate this duration. This application note describes how to calculate the duration of the CCEN for the MAX9257/MAX9258 SerDes chipset. The calculation is based on STO timeout, clock frequency, and UART bit timing. The CCEN duration is programmable and can be closed if not in use.
Designing Boards with Atmel AT89C51,AT89C52, AT89C1051, and AT89C2051 for Writing Flash at In-Circuit Test.
Recent improvements in chips and testers have made it possible for the tester to begin taking over the role tradi-tionally assigned to the PROM program-mer. Instead of having a PROM pro- grammer write nonvolatile memories before assembling the board, the in-cir- cuit tester writes them during in-circuit testing operations. Many Teradyne Z18- series testers are now in use loading code into nonvolatile memories, micro- controllers and in-circuit programmable logic devices. The purpose of this note is to explain how the Z18 approaches the writing task for Atmel AT89C series IC’s, so that designers of boards using these chips can get the best results.
The bootloader is stored in the internal boot ROM memory (system memory) of STM32devices. It is programmed by ST during production. Its main task is to download theapplication program to the internal Flash memory through one of the available serialperipherals (USART, CAN, USB, etc.). A communication protocol is defined for each serialinterface, with a compatible command set and sequences
Using the XGATE for Manchester DecodingTable of Contents
1 Introduction 1.1 XGATE Module in S12X 2 Decoding Algorithm 3 Software Implementation 3.1 Frame Scheme 3.2 Operating Modes and Demo 3.3 Files Summary 3.4 Complete Mode Flowchart 4 Manchester Encoder 4.1 Devices Used 5 Conclusion Appendix A Noise Elements during RF Transmissions in the Manchester Decoding ImplementationA.1 Types of Noise A.2 Effects of Noise A.3 Workaround for Noise Effects
匯編器在微處理器的驗證和應用中舉足輕重，如何設計通用的匯編器一直是研究的熱點之一。本文提出了一種開放式的匯編器系統設計思想，在匯編語言與機器語言間插入中間代碼CMDL（code mapping description language）語言，打破匯編語言與機器語言的直接映射關系，由此建立起一套描述匯編語言與機器語言的開放式映射體系。基于此開放式映射體系開發了一套匯編器系統，具有較高層次上的通用性和可移植性。【關鍵詞】指令集，CMDL，匯編器，開放式
Design of Retargetable Assembler System Liu Ling Feng Wen Nan Wang Ying Chun Jiang An Ping Ji Li Jiu IME of Peking University, 100871【摘要】An assembler plays a very important role in the field of microprocessor verifications and applications, thus how to build a retargetable assembler system has been a hotspot in this field for long time. This paper presents a new method about the retargetable assembler system design.It provides a kind of language CMDL, code mapping description language. during the process of assembling, assembler languages are firstly translated to CMDL, and then mapped to the machine codes. In an other word, CMDL is inserted between assembler languages and machine codes during the translation procedure. As a medium code, CMDL has a lot of features, such as high extraction, strong descript capabilities. It can describe almost all attributes of assembler languages. By breaking the direct mapping relationship between assembler languages and machine codes, the complexities of machine codes are hided to the users, therefore, the new retargetable assembler system has higher retargetable level by converting the mapping from assembler languages and machine codes to assembler languages and CMDL, and implementationof it becomes easier. Based on the new mapping system structure, a retargetable assemblersystem is developed. It proved the whole system has good retargetability and implantability.【關鍵詞】instruction set, symbol table, assembler, lexical analysis, retargetability
The PCA9517 is a CMOS integrated circuit that provides level shifting between lowvoltage (down to 0.9 V) and higher voltage (2.7 V to 5.5 V) I2C-bus or SMBus applications.While retaining all the operating modes and features of the I2C-bus system during thelevel shifts, it also permits extension of the I2C-bus by providing bidirectional buffering forboth the data (SDA) and the clock (SCL) lines, thus enabling two buses of 400 pF. Usingthe PCA9517 enables the system designer to isolate two halves of a bus for both voltageand capacitance. The SDA and SCL pins are over voltage tolerant and arehigh-impedance when the PCA9517 is unpowered.
The PCA9519 is a 4-channel level translating I2C-bus/SMBus repeater that enables theprocessor low voltage 2-wire serial bus to interface with standard I2C-bus or SMBus I/O.While retaining all the operating modes and features of the I2C-bus system during thelevel shifts, it also permits extension of the I2C-bus by providing bidirectional buffering forboth the data (SDA) and the clock (SCL) lines, thus enabling the I2C-bus or SMBusmaximum capacitance of 400 pF on the higher voltage side. The SDA and SCL pins areover-voltage tolerant and are high-impedance when the PCA9519 is unpowered.
