基于FPGA數(shù)字電壓表的設(shè)計(jì) EDA是電子設(shè)計(jì)自動(dòng)化（electronic Design Automation）的縮寫，在20世紀(jì)60年代中期從計(jì)算機(jī)輔助設(shè)計(jì)（CAD）、計(jì)算機(jī)輔助制造（CAM）、計(jì)算機(jī)輔助測(cè)試（CAT）和計(jì)算機(jī)輔助工程（CAE）的概念發(fā)展而來(lái)的。 EDA技術(shù)就是以計(jì)算機(jī)為工具，設(shè)計(jì)者在EDA軟件平臺(tái)上，用硬件描述語(yǔ)言VHDL完成設(shè)計(jì)文件，然后由計(jì)算機(jī)自動(dòng)地完成邏輯編譯、化簡(jiǎn)、分割、綜合、優(yōu)化、布局、布線和仿真，直至對(duì)于特定目標(biāo)芯片的適配編譯、邏輯映射和編程下載等工作。本電壓表的電路設(shè)計(jì)正是用VHDL語(yǔ)言完成的 。此次設(shè)計(jì)采用的是Altera公司 的Quartus II 7.0軟件。本次設(shè)計(jì)的參考電壓為2.5V，精度為0.01V。此電壓表的設(shè)計(jì)特點(diǎn)為通過(guò)軟件編程下載到硬件實(shí)現(xiàn)，設(shè)計(jì)周期短，開發(fā)效率高。
標(biāo)簽： FPGA 數(shù)字電壓表 報(bào)告
上傳時(shí)間： 2013-10-22
上傳用戶：Shaikh
This white paper discusses how market trends, the need for increased productivity, and new legislation have accelerated the use of safety systems in industrial machinery. This TÜV-qualified FPGA design methodology is changing the paradigms of safety designs and will greatly reduce development effort, system complexity, and time to market. This allows FPGA users to design their own customized safety controllers and provides a significant competitive advantage over traditional microcontroller or ASIC-based designs. Introduction The basic motivation of deploying functional safety systems is to ensure safe operation as well as safe behavior in cases of failure. Examples of functional safety systems include train brakes, proximity sensors for hazardous areas around machines such as fast-moving robots, and distributed control systems in process automation equipment such as those used in petrochemical plants. The International Electrotechnical Commission’s standard, IEC 61508: “Functional safety of electrical/electronic/programmable electronic safety-related systems,” is understood as the standard for designing safety systems for electrical, electronic, and programmable electronic (E/E/PE) equipment. This standard was developed in the mid-1980s and has been revised several times to cover the technical advances in various industries. In addition, derivative standards have been developed for specific markets and applications that prescribe the particular requirements on functional safety systems in these industry applications. Example applications include process automation (IEC 61511), machine automation (IEC 62061), transportation (railway EN 50128), medical (IEC 62304), automotive (ISO 26262), power generation, distribution, and transportation. 圖Figure 1. Local Safety System
標(biāo)簽： FPGA 安全系統(tǒng)
上傳時(shí)間： 2013-11-14
上傳用戶：zoudejile
附件有二個(gè)文當(dāng)，都是dxp2004教程 ，第一部份DXP2004的相關(guān)快捷鍵，以及中英文對(duì)照的意思。第二部份細(xì)致的講解的如何使用DXP2004。 dxp2004教程第一部份： 目錄 1 快捷鍵 2 常用元件及封裝 7 創(chuàng)建自己的集成庫(kù) 12 板層介紹 14 過(guò)孔 15 生成BOM清單 16 頂層原理圖: 16 生成PCB 17 包地 18 電路板設(shè)計(jì)規(guī)則 18 PCB設(shè)計(jì)注意事項(xiàng) 20 畫板心得 22 DRC 規(guī)則英文對(duì)照 22 一、Error Reporting 中英文對(duì)照 22 A ： Violations Associated with Buses 有關(guān)總線電氣錯(cuò)誤的各類型（共 12 項(xiàng)） 22 B ：Violations Associated Components 有關(guān)元件符號(hào)電氣錯(cuò)誤（共 20 項(xiàng)） 22 C ： violations associated with document 相關(guān)的文檔電氣錯(cuò)誤（共 10 項(xiàng)） 23 D ： violations associated with nets 有關(guān)網(wǎng)絡(luò)電氣錯(cuò)誤（共 19 項(xiàng)） 23 E ： Violations associated with others 有關(guān)原理圖的各種類型的錯(cuò)誤 (3 項(xiàng) ) 24 二、 Comparator 規(guī)則比較 24 A ： Differences associated with components 原理圖和 PCB 上有關(guān)的不同 ( 共 16 項(xiàng) ) 24 B ： Differences associated with nets 原理圖和 PCB 上有關(guān)網(wǎng)絡(luò)不同（共 6 項(xiàng)） 25 C ： Differences associated with parameters 原理圖和 PCB 上有關(guān)的參數(shù)不同（共 3 項(xiàng)） 25 Violations Associated withBuses欄 —總線電氣錯(cuò)誤類型 25 Violations Associated with Components欄 ——元件電氣錯(cuò)誤類型 26 Violations Associated with documents欄 —文檔電氣連接錯(cuò)誤類型 27 Violations Associated with Nets欄 ——網(wǎng)絡(luò)電氣連接錯(cuò)誤類型 27 Violations Associated with Parameters欄 ——參數(shù)錯(cuò)誤類型 28 dxp2004教程第二部份 路設(shè)計(jì)自動(dòng)化（ electronic Design Automation ） EDA 指的就是將電路設(shè)計(jì)中各種工作交由計(jì)算機(jī)來(lái)協(xié)助完成。如電路圖（ Schematic ）的繪制，印刷電路板（ PCB ）文件的制作執(zhí)行電路仿真（ Simulation ）等設(shè)計(jì)工作。隨著電子工業(yè)的發(fā)展，大規(guī)模、超大規(guī)模集成電路的使用是電路板走線愈加精密和復(fù)雜。電子線路 CAD 軟件產(chǎn)生了， Protel 是突出的代表，它操作簡(jiǎn)單、易學(xué)易用、功能強(qiáng)大。 1.1 Protel 的產(chǎn)生及發(fā)展 1985 年 誕生 dos 版 Protel 1991 年 Protel for Widows 1998 年 Protel98 這個(gè) 32 位產(chǎn)品是第一個(gè)包含 5 個(gè)核心模塊的 EDA 工具 1999 年 Protel99 既有原理圖的邏輯功能驗(yàn)證的混合信號(hào)仿真，又有了 PCB 信號(hào)完整性 分析的板級(jí)仿真，構(gòu)成從電路設(shè)計(jì)到真實(shí)板分析的完整體系。 2000 年 Protel99se 性能進(jìn)一步提高，可以對(duì)設(shè)計(jì)過(guò)程有更大控制力。 2002 年 Protel DXP 集成了更多工具，使用方便，功能更強(qiáng)大。 1.2 Protel DXP 主要特點(diǎn) 1 、通過(guò)設(shè)計(jì)檔包的方式，將原理圖編輯、電路仿真、 PCB 設(shè)計(jì)及打印這些功能有機(jī)地結(jié)合在一起，提供了一個(gè)集成開發(fā)環(huán)境。 2 、提供了混合電路仿真功能，為設(shè)計(jì)實(shí)驗(yàn)原理圖電路中某些功能模塊的正確與否提供了方便。 3 、提供了豐富的原理圖組件庫(kù)和 PCB 封裝庫(kù)，并且為設(shè)計(jì)新的器件提供了封裝向?qū)С绦颍?jiǎn)化了封裝設(shè)計(jì)過(guò)程。 4 、提供了層次原理圖設(shè)計(jì)方法，支持“自上向下”的設(shè)計(jì)思想，使大型電路設(shè)計(jì)的工作組開發(fā)方式成為可能。 5 、提供了強(qiáng)大的查錯(cuò)功能。原理圖中的 ERC （電氣法則檢查）工具和 PCB 的 DRC （設(shè)計(jì)規(guī)則檢查）工具能幫助設(shè)計(jì)者更快地查出和改正錯(cuò)誤。 6 、全面兼容 Protel 系列以前版本的設(shè)計(jì)文件，并提供了 OrCAD 格式文件的轉(zhuǎn)換功能。 7 、提供了全新的 FPGA 設(shè)計(jì)的功能，這好似以前的版本所沒有提供的功能。
上傳時(shí)間： 2015-01-01
上傳用戶：zhyfjj
Introduction to Xilinx Packaging electronic packages are interconnectable housings for semiconductor devices. The major functions of the electronic packages are to provide electrical interconnections between the IC and the board and to efficiently remove heat generated by the device. Feature sizes are constantly shrinking, resulting in increased number of transistors being packed into the device. Today's submicron technology is also enabling large-scale functional integration and system-on-a-chip solutions. In order to keep pace with these new advancements in silicon technologies, semiconductor packages have also evolved to provide improved device functionality and performance. Feature size at the device level is driving package feature sizes down to the design rules of the early transistors. To meet these demands, electronic packages must be flexible to address high pin counts, reduced pitch and form factor requirements. At the same time,packages must be reliable and cost effective.
上傳時(shí)間： 2013-11-21
上傳用戶：不懂夜的黑
EDA （electronic Design Automation）即“電子設(shè)計(jì)自動(dòng)化”，是指以計(jì)算機(jī)為工作平臺(tái)，以EDA軟件為開發(fā)環(huán)境，以硬件描述語(yǔ)言為設(shè)計(jì)語(yǔ)言，以可編程器件PLD為實(shí)驗(yàn)載體(包括CPLD、FPGA、EPLD等)，以集成電路芯片為目標(biāo)器件的電子產(chǎn)品自動(dòng)化設(shè)計(jì)過(guò)程。“工欲善其事，必先利其器”，因此，EDA工具在電子系統(tǒng)設(shè)計(jì)中所占的份量越來(lái)越高。下面就介紹一些目前較為流行的EDA工具軟件。 PLD 及IC設(shè)計(jì)開發(fā)領(lǐng)域的EDA工具，一般至少要包含仿真器（Simulator）、綜合器（Synthesizer）和配置器（Place and Routing, P&R）等幾個(gè)特殊的軟件包中的一個(gè)或多個(gè)，因此這一領(lǐng)域的EDA工具就不包括Protel、PSpice、Ewb等原理圖和PCB板設(shè)計(jì)及電路仿真軟件。目前流行的EDA工具軟件有兩種分類方法：一種是按公司類別進(jìn)行分類，另一種是按功能進(jìn)行劃分。 若按公司類別分，大體可分兩類：一類是EDA 專業(yè)軟件公司，業(yè)內(nèi)最著名的三家公司是Cadence、Synopsys和Mentor Graphics；另一類是PLD器件廠商為了銷售其產(chǎn)品而開發(fā)的EDA工具，較著名的公司有Altera、Xilinx、lattice等。前者獨(dú)立于半導(dǎo)體器件廠商，具有良好的標(biāo)準(zhǔn)化和兼容性，適合于學(xué)術(shù)研究單位使用，但系統(tǒng)復(fù)雜、難于掌握且價(jià)格昂貴；后者能針對(duì)自己器件的工藝特點(diǎn)作出優(yōu)化設(shè)計(jì)，提高資源利用率，降低功耗，改善性能，比較適合產(chǎn)品開發(fā)單位使用。 若按功能分，大體可以分為以下三類。 (1) 集成的PLD/FPGA開發(fā)環(huán)境 由半導(dǎo)體公司提供，基本上可以完成從設(shè)計(jì)輸入（原理圖或HDL）→仿真→綜合→布線→下載到器件等囊括所有PLD開發(fā)流程的所有工作。如Altera公司的MaxplusⅡ、QuartusⅡ，Xilinx公司的ISE，Lattice公司的 ispDesignExpert等。其優(yōu)勢(shì)是功能全集成化，可以加快動(dòng)態(tài)調(diào)試，縮短開發(fā)周期；缺點(diǎn)是在綜合和仿真環(huán)節(jié)與專業(yè)的軟件相比，都不是非常優(yōu)秀的。 (2) 綜合類 這類軟件的功能是對(duì)設(shè)計(jì)輸入進(jìn)行邏輯分析、綜合和優(yōu)化，將硬件描述語(yǔ)句（通常是系統(tǒng)級(jí)的行為描述語(yǔ)句）翻譯成最基本的與或非門的連接關(guān)系（網(wǎng)表），導(dǎo)出給PLD/FPGA廠家的軟件進(jìn)行布局和布線。為了優(yōu)化結(jié)果，在進(jìn)行較復(fù)雜的設(shè)計(jì)時(shí)，基本上都使用這些專業(yè)的邏輯綜合軟件，而不采用廠家提供的集成PLD/FPGA開發(fā)工具。如Synplicity公司的Synplify、Synopsys公司的FPGAexpress、FPGA Compiler Ⅱ等。 (3) 仿真類 這類軟件的功能是對(duì)設(shè)計(jì)進(jìn)行模擬仿真，包括布局布線（P&R）前的“功能仿真”（也叫“前仿真”）和P&R后的包含了門延時(shí)、線延時(shí)等的“時(shí)序仿真”（也叫“后仿真”）。復(fù)雜一些的設(shè)計(jì)，一般需要使用這些專業(yè)的仿真軟件。因?yàn)橥瑯拥脑O(shè)計(jì)輸入，專業(yè)軟件的仿真速度比集成環(huán)境的速度快得多。此類軟件最著名的要算Model Technology公司的Modelsim，Cadence公司的NC-Verilog/NC-VHDL/NC-SIM等。 以上介紹了一些具代表性的EDA 工具軟件。它們?cè)谛阅苌细饔兴L(zhǎng)，有的綜合優(yōu)化能力突出，有的仿真模擬功能強(qiáng)，好在多數(shù)工具能相互兼容，具有互操作性。比如Altera公司的 QuartusII集成開發(fā)工具，就支持多種第三方的EDA軟件，用戶可以在QuartusII軟件中通過(guò)設(shè)置直接調(diào)用Modelsim和 Synplify進(jìn)行仿真和綜合。 如果設(shè)計(jì)的硬件系統(tǒng)不是很大，對(duì)綜合和仿真的要求不是很高，那么可以在一個(gè)集成的開發(fā)環(huán)境中完成整個(gè)設(shè)計(jì)流程。如果要進(jìn)行復(fù)雜系統(tǒng)的設(shè)計(jì)，則常規(guī)的方法是多種EDA工具協(xié)調(diào)工作，集各家之所長(zhǎng)來(lái)完成設(shè)計(jì)流程。
上傳時(shí)間： 2013-10-11
上傳用戶：1079836864
Design techniques for electronic systems areconstantly changing. In industries at the heart of thedigital revolution, this change is especially acute.Functional integration, dramatic increases incomplexity, new standards and protocols, costconstraints, and increased time-to-market pressureshave bolstered both the design challenges and theopportunities to develop modern electronic systems.One trend driving these changes is the increasedintegration of core logic with previously discretefunctions to achieve higher performance and morecompact board designs.
標(biāo)簽： System Xilinx FPGA 151
上傳時(shí)間： 2013-11-23
上傳用戶：kangqiaoyibie
Xilinx is disclosing this user guide, manual, release note, and/or specification (the "Documentation") to you solely for use in the developmentof designs to operate with Xilinx hardware devices. You may not reproduce, distribute, republish, download, display, post, or transmit theDocumentation in any form or by any means including, but not limited to, electronic, mechanical, photocopying, recording, or otherwise,without the prior written consent of Xilinx. Xilinx expressly disclaims any liability arising out of your use of the Documentation. Xilinx reservesthe right, at its sole discretion, to change the Documentation without notice at any time. Xilinx assumes no obligation to correct any errorscontained in the Documentation, or to advise you of any corrections or updates. Xilinx expressly disclaims any liability in connection withtechnical support or assistance that may be provided to you in connection with the Information.
標(biāo)簽： Virtex FPGA PCB 設(shè)計(jì)手冊(cè)
上傳時(shí)間： 2013-11-11
上傳用戶：zwei41
This document was developed under the Standard Hardware and Reliability Program (SHARP) TechnologyIndependent Representation of electronic Products (TIREP) project. It is intended for use by VHSIC HardwareDescription Language (VHDL) design engineers and is offered as guidance for the development of VHDL modelswhich are compliant with the VHDL Data Item Description (DID DI-EGDS-80811) and which can be providedto manufacturing engineering personnel for the development of production data and the subsequent productionof hardware. Most VHDL modeling performed to date has been concentrated at either the component level orat the conceptual system level. The assembly and sub-assembly levels have been largely disregarded. Under theSHARP TIREP project, an attempt has been made to help close this gap. The TIREP models are based upon lowcomplexity Standard electronic Modules (SEM) of the format A configuration. Although these modules are quitesimple, it is felt that the lessons learned offer guidance which can readily be applied to a wide range of assemblytypes and complexities.
標(biāo)簽： Modelling Guide Navy VHDL
上傳時(shí)間： 2013-11-20
上傳用戶：pzw421125
Xilinx is disclosing this user guide, manual, release note, and/or specification (the “Documentation”) to you solely for use in the development of designs to operate with Xilinx hardware devices. You may not reproduce, distribute, republish, download, display, post, or transmit the Documentation in any form or by any means including, but not limited to, electronic, mechanical, photocopying, recording, or otherwise, without the prior written consent of Xilinx. Xilinx expressly disclaims any liability arising out of your use of the Documentation. Xilinx reserves the right, at its sole discretion, to change the Documentation without notice at any time. Xilinx assumes no obligation to correct any errors contained in the Documentation, or to advise you of any corrections or updates. Xilinx expressly disclaims any liability in connection with technical support or assistance that may be provided to you in connection with the Information.
標(biāo)簽： CPLD
上傳時(shí)間： 2014-12-05
上傳用戶：qazxsw
Abstract: This application note presents an overview of electronic margining and its value in detectingpotential system failures before a product ships from the factory. It is a calibration method that effectivelypredicts and allows adjustments to improve product quality. Margining also can be used to sort productsinto performance levels, allowing premium products to be sold at premium prices. We discuss thedownside of sorting and suggest alternative ways to segregate products.
標(biāo)簽： 產(chǎn)品檢測(cè) 校準(zhǔn)
上傳時(shí)間： 2014-01-22
上傳用戶：lhw888
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