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隊列函數queue

參照棧類模板的例子編寫一個隊列類模板class <T> Queue，私有成員包括：隊首指針Front，隊尾指針Tail，隊列容積max。實現：構造函數Queue，復制構造函數Queue，析構函數~Queue，入隊函數In，出隊函數Out（每次出隊，后面的元素自動前移一位），判隊列空函數empty。并分別用隊列類模板定義int和double對象，通過實例調用各個成員函數。

標簽： Queue 函數 double class Front empty 隊列 Tail 模板 Out

上傳時間： 2020-05-04

上傳用戶：1qw2e3r4t5y6u7i8
Intelligence_-A-Modern-Approach

Artificial Intelligence (AI) is a big field, and this is a big book. We have tried to explore the full breadth of the field, which encompasses logic, probability, and continuous mathematics; perception, reasoning, learning, and action; and everything from microelectronic devices to robotic planetary explorers. The book is also big because we go into some depth. The subtitle of this book is “A Modern Approach.” The intended meaning of this rather empty phrase is that we have tried to synthesize what is now known into a common frame- work, rather than trying to explain each subfield of AI in its own historical context. We apologize to those whose subfields are, as a result, less recognizable.

標簽： A-Modern-Approach Intelligence

上傳時間： 2020-06-10

上傳用戶：shancjb
FPGA片內FIFO讀寫測試Verilog邏輯源碼Quartus工程文件+文檔說明使用 FPGA

FPGA片內FIFO讀寫測試Verilog邏輯源碼Quartus工程文件+文檔說明，使用 FPGA 內部的 FIFO 以及程序對該 FIFO 的數據讀寫操作。FPGA型號Cyclone4E系列中的EP4CE6F17C8，Quartus版本17.1。timescale 1ns / 1ps//////////////////////////////////////////////////////////////////////////////////module fifo_test( input clk, //50MHz時鐘 input rst_n //復位信號，低電平有效 );//-----------------------------------------------------------localparam W_IDLE = 1;localparam W_FIFO = 2; localparam R_IDLE = 1;localparam R_FIFO = 2; reg[2:0] write_state;reg[2:0] next_write_state;reg[2:0] read_state;reg[2:0] next_read_state;reg[15:0] w_data; //FIFO寫數據wire wr_en; //FIFO寫使能wire rd_en; //FIFO讀使能wire[15:0] r_data; //FIFO讀數據wire full; //FIFO滿信號 wire empty; //FIFO空信號 wire[8:0] rd_data_count; wire[8:0] wr_data_count; ///產生FIFO寫入的數據always@(posedge clk or negedge rst_n)begin if(rst_n == 1'b0) write_state <= W_IDLE; else write_state <= next_write_state;endalways@(*)begin case(write_state) W_IDLE: if(empty == 1'b1) //FIFO空，開始寫FIFO next_write_state <= W_FIFO; else next_write_state <= W_IDLE; W_FIFO: if(full == 1'b1) //FIFO滿 next_write_state <= W_IDLE; else next_write_state <= W_FIFO; default: next_write_state <= W_IDLE; endcaseendassign wr_en = (next_write_state == W_FIFO) ? 1'b1 : 1'b0; always@(posedge clk or negedge rst_n)begin if(rst_n == 1'b0) w_data <= 16'd0; else if (wr_en == 1'b1) w_data <= w_data + 1'b1; else w_data <= 16'd0; end///產生FIFO讀的數據always@(posedge clk or negedge rst_n)begin if(rst_n == 1'b0) read_state <= R_IDLE; else read_state <= next_read_state;endalways@(*)begin case(read_state) R_IDLE: if(full == 1'b1) //FIFO滿, 開始讀FIFO next_read_state <= R_FIFO; else next_read_state <= R_IDLE; R_FIFO: if(empty == 1'b1)

標簽： fpga fifo verilog quartus

上傳時間： 2021-12-19

上傳用戶：20125101110
IAR for ARM7.1建立STM32的項目工程

一、建立基本的項目平臺在建項目平臺前需要做一些準備，選擇一個盤建立 Platform”文件夾，在Platform"文件夾下建boot".HardWareTest"、"Project"、"Src"四個文件夾，boot"用來存放bootloader工程程序，HardWareTest"用來存放硬件自動測試工程程序，"Project"用來存放項目平臺建立時生產的文件，"Src"用來存放STM32uCOSl工程的應用程序。下面開始建項目平臺吧。步驟一：新建一個 IAR for ARM工程，File-> New-> Workspac創建一個新的工作空間，然后通過Project >Create New Project建立一個ARM的empty project，點擊“OK"后彈出工程保存菜單，填寫工程名“STM32uCOSI"，然后點擊“保存”，第一個工程建立完畢。步驟二：再建一個工程，通過Project > Create New Project建立一個ARM的empty project，點擊“OK"后彈出工程保存菜單，填寫工程名“BOOT"，然后點擊“保存”，第二個工程建立完畢。步驟三：建第三個工程，通過Project →> Create New Project建立一個ARM的empty project，點擊“OK"后彈出工程保存菜單，填寫工程名“HardWareTest"，然后點擊“保存"，第三個工程建立完畢。

標簽： iar stm32

上傳時間： 2022-06-26

上傳用戶：