Aodv for NS-2. A mobile ad-hoc network (MANET) is a kind of wireless ad-hoc network, and is a self-configuring
network of mobile routers connected wirelessly. MANET may operate in a standalone fashion, or may
be connected to the larger Internet. Many routing protocols have been developed for MANETs over
the past few years. This project evaluated three specific MANET routing protocols which are Ad-hoc
On-demand Distance Vector (AODV), Dynamic Source Routing (DSR) and Dynamic MANET Ondemand
routing protocol (DYMO) to better understand the major characteristics of these routing
protocols. Different performance aspects were investigated in this project including packet delivery
ratio, routing overhead, throughput and average end-to-end delay.
This document provides practical, common guidelines for incorporating PCI Express interconnect
layouts onto Printed Circuit Boards (PCB) ranging from 4-layer desktop baseboard designs to 10-
layer or more server baseboard designs. Guidelines and constraints in this document are intended
for use on both baseboard and add-in card PCB designs. This includes interconnects between PCI
Express devices located on the same baseboard (chip-to-chip routing) and interconnects between
a PCI Express device located “down” on the baseboard and a device located “up” on an add-in
card attached through a connector.
This document is intended to cover all major components of the physical interconnect including
design guidelines for the PCB traces, vias and AC coupling capacitors, as well as add-in card
edge-finger and connector considerations. The intent of the guidelines and examples is to help
ensure that good high-speed signal design practices are used and that the timing/jitter and
loss/attenuation budgets can also be met from end-to-end across the PCI Express interconnect.
However, while general physical guidelines and suggestions are given, they may not necessarily
guarantee adequate performance of the interconnect for all layouts and implementations.
Therefore, designers should consider modeling and simulation of the interconnect in order to
ensure compliance to all applicable specifications.
The document is composed of two main sections. The first section provides an overview of
general topology and interconnect guidelines. The second section concentrates on physical layout
constraints where bulleted items at the beginning of a topic highlight important constraints, while
the narrative that follows offers additional insight.
Abstract: A resistive feedback network is often used to set the output voltage of a power supply. A mechanical potentiometer (pot)conveniently solves the problem of adjusting a power supply. For easier automatic calibration, a mechanical pot can be replaced witha digital pot. This application note presents a calibration solution that uses a digital pot, because digipots are smaller, do not movewith age or vibration, and can be recalibrated remotely. This proposed solution reduces the susceptibility of the system to thetolerance of the digital pot's end-to-end resistance, making the solution optimal fordesigners. This application note also explainssome of the equations required to calculate the resistor chain values and to use a digital pot in this way. A spreadsheet withstandard reisistor values is available for easy calculations.
在理論分析循環碼編碼和譯碼基本原理的基礎上，提出了基于單片機系統的(24，16)循環碼軟件實現編碼、譯碼的方案。仿真結果表明(24，16)循環碼能有效地克服來自通訊信道的干擾，保證數據通信的可靠及系統的穩定，使誤碼率大幅度降低。本論文對(24，16)循環碼的研究結果表明，可以有效地降低錯誤概率和提高系統的吞吐量，實現糾錯僅需要在接收端增加有限的存儲空間和計算復雜度，具有一定的實用價值。
Abstract:
Based on analyzing the theory of encoding and decoding of cyclic code， this paper showed the schemes of encoding and decoding of(24，16)cyclic code by the software and based on microcontroller. Simulation results show that using (24，16) cyclic codes can effectively overcome the interference from communication channel， ensure the reliability and stability of data communication systems， and reduce the bit error rate greatly. The results of this paper show that by using the (24，16) cyclic code， the error rate can be reduced and the system throughput can be improved. Meanwhile， the system only needs to enlarge limited storage space and computation the complexity at the receiving end to realize error correction. Thus the (24，16) cyclic code has a practical value.
This document provides practical, common guidelines for incorporating PCI Express interconnect
layouts onto Printed Circuit Boards (PCB) ranging from 4-layer desktop baseboard designs to 10-
layer or more server baseboard designs. Guidelines and constraints in this document are intended
for use on both baseboard and add-in card PCB designs. This includes interconnects between PCI
Express devices located on the same baseboard (chip-to-chip routing) and interconnects between
a PCI Express device located “down” on the baseboard and a device located “up” on an add-in
card attached through a connector.
This document is intended to cover all major components of the physical interconnect including
design guidelines for the PCB traces, vias and AC coupling capacitors, as well as add-in card
edge-finger and connector considerations. The intent of the guidelines and examples is to help
ensure that good high-speed signal design practices are used and that the timing/jitter and
loss/attenuation budgets can also be met from end-to-end across the PCI Express interconnect.
However, while general physical guidelines and suggestions are given, they may not necessarily
guarantee adequate performance of the interconnect for all layouts and implementations.
Therefore, designers should consider modeling and simulation of the interconnect in order to
ensure compliance to all applicable specifications.
The document is composed of two main sections. The first section provides an overview of
general topology and interconnect guidelines. The second section concentrates on physical layout
constraints where bulleted items at the beginning of a topic highlight important constraints, while
the narrative that follows offers additional insight.
3GPP文件格式標準，英文版。
3rd Generation Partnership Project
Technical Specification Group Services and System Aspects Transparent end-to-end
packet switched streaming service (PSS)
3GPP file format (3GP)
(Release 6)
pashload是應用在linux下的網絡帶寬測試源程序精確度比較高
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Pathload is a tool for estimating the available bandwidth
of an end-to-end path from a host S (sender) to a host R (receiver).
The available bandwidth is the maximum IP-layer
throughput that a flow can get in the path from S to R,
without reducing the rate of the rest of the traffic in the path.
