First end second order sigma-delta ADC Simulink model.
標(biāo)簽： sigma-delta Simulink second First
上傳時(shí)間： 2014-01-03
上傳用戶(hù)：啊颯颯大師的
The UMTS Physical Layer model consists of an end-to-end (transmitter-to-receiver) simulation of the Frequency Division Duplex (FDD) Downlink physical layer for several Dedicated Channels (DCH) as specified by the 3GPP standard (Release 99).
標(biāo)簽： transmitter-to-receiver end-to-end simulation Physical
上傳時(shí)間： 2014-01-11
上傳用戶(hù)：it男一枚
how to search for the biggest end folder from your sistem (under Linux)
標(biāo)簽： biggest folder search sistem
上傳時(shí)間： 2013-12-19
上傳用戶(hù)：TF2015
document for upload and download will contains the end note and upload upload upload upload upload upload upload upload upload upload
標(biāo)簽： upload and document contains
上傳時(shí)間： 2014-01-13
上傳用戶(hù)：hj_18
國(guó)產(chǎn)仿三菱PLC源代碼 /* _LD,_LDI,_AND,_ANI,_OR,_ORI,_INV,_OUT(_OUT_T,_OUT_C),_SET,_RST,_ANB,_ORB,_LDP,_LDF,_ANDP,_ANDF, */ /* _ORP,_ORF,_PLS,_PLF,_MPS,_MRD,_MPP,_NOP,end,_ADD,_SUB,_MUL,_DIV,_INC,_DEC,_WAND,_WOR,_WXOR, */ /* _NEG,_ALT,_MOV,_CML,_XCH,_BCD,_BIN,_CMP,_ZCP,_FMOV,_ROR,_ROL,_ZRST,_REF,_ASCI,_SWAP,_CJ,_CALL, */ /* _SRET,_Fend,_LD>=,_LD,_LD=,_AND,_AND=,_OR,_OR
上傳時(shí)間： 2013-07-28
上傳用戶(hù)：sssl
Abstract: This application note describes the essential workings of an electrocardiogram (ECG). It discussesfactors that disrupt the ECG signals and make reliable, highly-accurate electrical characterization difficult. Theindustry-standard solution for ECG electrical characterization, which uses an analog front-end and ADCcombination, is explained. The article then introduces the MAX11040 simultaneous-sampling, sigma-deltaADC as a compelling, highly integrated solution that eliminates the need for the AFE, and saves both spaceand cost for the application.
標(biāo)簽： ADC 24位 心電圖 中的應(yīng)用
上傳時(shí)間： 2013-12-23
上傳用戶(hù)：sssl
Abstract: This tutorial discusses proper printed-circuit board (PCB) grounding for mixed-signal designs. Formost applications a simple method without cuts in the ground plane allows for successful PCB layouts withthis kind of IC. We begin this document with the basics: where the current flows. Later, we describe how toplace components and route signal traces to minimize problems with crosstalk. Finally, we move on toconsider power supply-currents and end by discussing how to extend what we have learned to circuits withmultiple mixed-signal ICs.
標(biāo)簽： PCB 正 印刷電路板 混合信號(hào)
上傳時(shí)間： 2013-11-04
上傳用戶(hù)：pol123
Portable, battery-powered operation of electronic apparatushas become increasingly desirable. Medical, remotedata acquisition, power monitoring and other applicationsare good candidates for battery operation. In some circumstances,due to space, power or reliability considerations,it is preferable to operate the circuitry from a single 1.5Vcell. Unfortunately, a 1.5V supply eliminates almost alllinear ICs as design candidates. In fact, the LM10 opamp-reference and the LT®1017/LT1018 comparators arethe only IC gain blocks fully specifi ed for 1.5V operation.Further complications are presented by the 600mV dropof silicon transistors and diodes. This limitation consumesa substantial portion of available supply range, makingcircuit design diffi cult. Additionally, any circuit designedfor 1.5V operation must function at end-of-life batteryvoltage, typically 1.3V. (See Box Section, “Componentsfor 1.5V Operation.”)
標(biāo)簽： Circuitry Operation Single 1017
上傳時(shí)間： 2013-12-20
上傳用戶(hù)：Wwill
enter——選取或啟動(dòng) esc——放棄或取消 f1——啟動(dòng)在線(xiàn)幫助窗口 tab——啟動(dòng)浮動(dòng)圖件的屬性窗口 pgup——放大窗口顯示比例 pgdn——縮小窗口顯示比例 end——刷新屏幕 del——刪除點(diǎn)取的元件（1個(gè)） ctrl+del——刪除選取的元件（2個(gè)或2個(gè)以上） x+a——取消所有被選取圖件的選取狀態(tài) x——將浮動(dòng)圖件左右翻轉(zhuǎn) y——將浮動(dòng)圖件上下翻轉(zhuǎn) space——將浮動(dòng)圖件旋轉(zhuǎn)90度 crtl+ins——將選取圖件復(fù)制到編輯區(qū)里 shift+ins——將剪貼板里的圖件貼到編輯區(qū)里 shift+del——將選取圖件剪切放入剪貼板里 alt+backspace——恢復(fù)前一次的操作 ctrl+backspace——取消前一次的恢復(fù) crtl+g——跳轉(zhuǎn)到指定的位置 crtl+f——尋找指定的文字
上傳時(shí)間： 2013-12-29
上傳用戶(hù)：13033095779
This document provides practical, common guidelines for incorporating PCI Express interconnect layouts onto Printed Circuit Boards (PCB) ranging from 4-layer desktop baseboard designs to 10- layer or more server baseboard designs. Guidelines and constraints in this document are intended for use on both baseboard and add-in card PCB designs. This includes interconnects between PCI Express devices located on the same baseboard (chip-to-chip routing) and interconnects between a PCI Express device located “down” on the baseboard and a device located “up” on an add-in card attached through a connector. This document is intended to cover all major components of the physical interconnect including design guidelines for the PCB traces, vias and AC coupling capacitors, as well as add-in card edge-finger and connector considerations. The intent of the guidelines and examples is to help ensure that good high-speed signal design practices are used and that the timing/jitter and loss/attenuation budgets can also be met from end-to-end across the PCI Express interconnect. However, while general physical guidelines and suggestions are given, they may not necessarily guarantee adequate performance of the interconnect for all layouts and implementations. Therefore, designers should consider modeling and simulation of the interconnect in order to ensure compliance to all applicable specifications. The document is composed of two main sections. The first section provides an overview of general topology and interconnect guidelines. The second section concentrates on physical layout constraints where bulleted items at the beginning of a topic highlight important constraints, while the narrative that follows offers additional insight.
標(biāo)簽： pci PCB 設(shè)計(jì)規(guī)范
上傳時(shí)間： 2013-10-15
上傳用戶(hù)：busterman
蟲(chóng)蟲(chóng)下載站版權(quán)所有 京ICP備2021023401號(hào)-1
