BurchED B5-X300 Spartan2e using XC2S300e device Top level file for 6809 compatible system on a chip Designed with Xilinx XC2S300e Spartan 2+ FPGA. Implemented With BurchED B5-X300 FPGA board, B5-SRAM module, B5-CF module and B5-FPGA-CPU-IO module
標(biāo)簽： compatible 300 Spartan2e BurchED
上傳時(shí)間： 2015-07-07
上傳用戶：star_in_rain
liblinphone is a high level library to make a SIP phone. This library includes ALL the features of linphone. It is designed to be easy to use, directly from a user interface.
標(biāo)簽： library liblinphone features includes
上傳時(shí)間： 2014-01-08
上傳用戶：qq521
1)Learn more about the capabilities in Quartus: 2)Learn to use different design entry techniques 2)Design entry methods available within Quartus Text editor,Block diagram/schematic file editor, Quartus interface with design entry/synthesis tools from Exemplar, Synopsys, Synplicity and Viewlogic
標(biāo)簽： Learn capabilities techniques different
上傳時(shí)間： 2014-01-18
上傳用戶：yxgi5
c Language High Level Programming
標(biāo)簽： Programming Language Level High
上傳時(shí)間： 2015-07-19
上傳用戶：hullow
a java e book for a new guy to learn and teach u from low to high level
標(biāo)簽： learn level teach java
上傳時(shí)間： 2013-11-30
上傳用戶：fnhhs
/* Check_SST_39VF400A Check manufacturer and device ID /* CFI_Query CFI Query Entry/Exit command sequence /* Erase_One_Sector Erase a sector of 2048 words /* Erase_One_Block Erase a block of 32K words /* Erase_Entire_Chip Erase the contents of the entire chip /* Program_One_Word Alter data in one word /* Program_One_Sector Alter data in 2048 word sector /* Program_One_Block Alter data in 32K word block
標(biāo)簽： manufacturer Check_SST CFI_Query command
上傳時(shí)間： 2013-12-15
上傳用戶：jjj0202
//Basic packet sending test at the MAC level, used for internal testing only. //This packet test has one node sending out a variety of //differently formatted packets to two assumed destination nodes.
標(biāo)簽： packet test internal sending
上傳時(shí)間： 2014-08-21
上傳用戶：CSUSheep
輸入：為需要壓縮圖象的名稱(chēng),該主程序僅能構(gòu)處理256灰度圖,讀者可以自行改編為RGB處理；ratio為壓縮比率；level為小波分解的級(jí)數(shù) 輸出:是解壓完畢的圖象數(shù)據(jù)矩陣
上傳時(shí)間： 2013-12-14
上傳用戶：diets
VHDL intermediate Level,僅供學(xué)習(xí)使用
標(biāo)簽： intermediate Level VHDL
上傳時(shí)間： 2014-12-05
上傳用戶：iswlkje
體現(xiàn)了lod(level of detail)算法 包括網(wǎng)格細(xì)分,空間層次
上傳時(shí)間： 2014-08-12
上傳用戶：zjf3110
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