基于Verilog-HDL的硬件電路的實現 9.7 步進電機的控制 9.7.1 步進電機驅動的邏輯符號 9.7.2 步進電機驅動的時序圖 9.7.3 步進電機驅動的邏輯框圖 9.7.4 計數模塊的設計與實現 9.7.5 譯碼模塊的設計與實現 9.7.6 步進電機驅動的Verilog-HDL描述 9.7.7 編譯指令-"宏替換`define"的使用方法 9.7.8 編譯指令-"時間尺度`timescale"的使用方法 9.7.9 系統任務-"$finish"的使用方法 9.7.10 步進電機驅動的硬件實現
標簽： Verilog-HDL 步進電機驅動 9.7 硬件電路
上傳時間： 2014-01-23
上傳用戶：拔絲土豆
Jode Decompiler.安裝方法：點擊Eclipse的Help菜單 --> Software Updates --> Find and install...，然后選擇：Search for new features to install，在彈出的對話框中點擊"New Remote Site..."菜單。填入：Name: Jode DecomopilerURL: http://www.technoetic.com/eclipse/update點擊"finish"。之后可以在Window菜單的Preferences --> Java -->Jode Decompiler中配置插件的信息。
標簽： Decompiler Software Eclipse Updates
上傳時間： 2015-11-19
上傳用戶：cuibaigao
First of all we would like to thank God Almighty for giving us the strength and confidence in pursing the ambitions. We would like to thank our Examiner Professor Axel Jantsch for allowing us to do this under his guidance and encouragement. At the same time we would like to mention our sincere thanks to Mr. Said Zainali, Manager of FRAME ACCESS AB for giving all the required equipment and the technical support which helped us to finish this thesis. We would like to mention our gratitude to our fellow VACS team members who helped us a lot during difficult times.
標簽： confidence Almighty strength giving
上傳時間： 2013-12-01
上傳用戶：小碼農lz
看n2實例 #Create a simulator object set ns [new Simulator] #Define different colors for data flows #$ns color 1 Blue #$ns color 2 Red #Open the nam trace file set nf [open out-1.nam w] $ns namtrace-all $nf set f0 [open out0.tr w] set f1 [open out1.tr w] #Define a finish procedure proc finish {} { global ns nf $ns flush-trace #Close the trace file close $nf #Execute nam on the trace file exit 0 } #Create four nodes set n0 [$ns node] set n1 [$ns node] set n2 [$ns node] set n3 [$ns node] #Create links between the nodes $ns duplex-link $n0 $n2 1Mb 10ms
標簽： simulator Simulator different Create
上傳時間： 2016-07-02
上傳用戶：wfl_yy
SOPC實驗--Hello World實驗:啟動Quartus II軟件，選擇File→New Project Wizard，在出現的對話框中填寫項目名稱 2、 點擊finish，然后選擇“是”。選擇Assignments→Device，改寫各項內容。Family改為CycloneII，根據實驗板上的器件選擇相應的器件，本實驗選擇EP2C5T144C8,點擊對話框中的Device & Pin Options，在Configuration中，選項Use Configuration Device為EPCS1，選項Unused Pins為As inputs,tri-stated.
上傳時間： 2014-01-13
上傳用戶：梧桐
在采用多道程序設計的系統中，往往有若干個進程同時處于就緒狀態。當就緒進程個數大于處理機數時，就必須依照某種策略來決定哪些進程優先占用處理機。本實驗模擬在單處理機情況下的處理機調度，幫助學生加深了解處理機調度的工作。 二、實驗類型 設計型。 三、預習內容 預習課本處理機調度有關內容，包括進程占用處理機的策略方法。 四、實驗要求與提示 設計進程調度算法，進程數不定；包含幾種調度算法，并加以實現；輸出進程的調度過程——進程的狀態、鏈表等。要求使用優先權法和輪轉法模擬進程調度過程。 【提示】：簡化假設 1） 進程為計算型的（無I/O） 2） 進程狀態：ready、running、finish 3） 進程需要的CPU時間以時間片為單位確定 【提示】：算法描述 1） 優先權法——動態優先權，當前運行進程用完時間片后，其優先權減去一個常數。 2） 輪轉法
上傳時間： 2013-12-15
上傳用戶：duoshen1989
Learn how to leverage a key Java technology used to access relational data from Java programs, in an Oracle environment. Author Donald Bales begins by teaching you the mysteries of establishing database connections, and how to issue SQL queries and get results back. You ll move on to advanced topics such as streaming large objects, calling PL/procedures, and working with Oracle9i s object-oriented features, then finish with a look at transactions, concurrency management, and performance
標簽： Java technology relational leverage
上傳時間： 2017-08-02
上傳用戶：xz85592677
Using Trolltech s Qt you can build industrial-strength C++ applications that run natively on Windows, Linux/Unix, Mac OS X, and embedded Linux--without making source code changes. With this book Trolltech insiders have written a start-to-finish guide to getting great results with the most powerful version of Qt ever created: Qt 4.1.
標簽： industrial-strength applications Trolltech natively
上傳時間： 2017-08-11
上傳用戶：邶刖
The running time of quicksort can be improved in practice by taking advantage of the fast running time of insertion sort when its input is “nearly” sorted. When quicksort is called on a subarray with fewer than k elements, let it simply return without sorting the subarray. After the top-level call to quicksort returns, run insertion sort on the entire array to finish the sorting process.
標簽： running advantage quicksort improved
上傳時間： 2013-12-01
上傳用戶：梧桐
基于FPGA設計的sdram讀寫測試實驗Verilog邏輯源碼Quartus工程文件+文檔說明，DRAM選用海力士公司的 HY57V2562 型號,容量為的 256Mbit,采用了 54 引腳的TSOP 封裝, 數據寬度都為 16 位, 工作電壓為 3.3V,并丏采用同步接口方式所有的信號都是時鐘信號。FPGA型號Cyclone4E系列中的EP4CE6F17C8，Quartus版本17.1。timescale 1ps/1psmodule top(input clk,input rst_n,output[1:0] led,output sdram_clk, //sdram clockoutput sdram_cke, //sdram clock enableoutput sdram_cs_n, //sdram chip selectoutput sdram_we_n, //sdram write enableoutput sdram_cas_n, //sdram column address strobeoutput sdram_ras_n, //sdram row address strobeoutput[1:0] sdram_dqm, //sdram data enable output[1:0] sdram_ba, //sdram bank addressoutput[12:0] sdram_addr, //sdram addressinout[15:0] sdram_dq //sdram data);parameter MEM_DATA_BITS = 16 ; //external memory user interface data widthparameter ADDR_BITS = 24 ; //external memory user interface address widthparameter BUSRT_BITS = 10 ; //external memory user interface burst widthparameter BURST_SIZE = 128 ; //burst sizewire wr_burst_data_req; // from external memory controller,write data request ,before data 1 clockwire wr_burst_finish; // from external memory controller,burst write finish
標簽： fpga sdram verilog quartus
上傳時間： 2021-12-18
上傳用戶：
