If you have not registered, Please [regist first].You should upload at least five sourcecodes/documents. (upload 5 files, you can download 200 files).
標簽： sourcecodes registered Please docume
上傳時間： 2014-01-07
上傳用戶：1109003457
If you have not registered, Please [regist first].You should upload at least five sourcecodes/documents. (upload 5 files, you can download 200 files).
標簽： sourcecodes registered Please docume
上傳時間： 2013-12-19
上傳用戶：litianchu
f you have not registered, Please [regist first].You should upload at least five sourcecodes/documents. (upload 5 files, you can download 200 files). Webmaster will activate your member account after checking your files. If you do not want to upload source code, you can join the [VIP member] to
標簽： sourcecodes registered documen Please
上傳時間： 2017-09-13
上傳用戶：ljmwh2000
f you have not registered, Please [regist first].You should upload at least five sourcecodes/documents. (upload 5 files, you can download 200 files). Webmaster will activate your member account after checking your files. If you do not want to upload source code, you can join the [VIP member] to
標簽： sourcecodes registered documen Please
上傳時間： 2014-01-16
上傳用戶：fandeshun
為解決輸油管道溫度壓力參數實時監測的問題，設計了以C8051F930單片機作為控制核心的超低功耗輸油管道溫度壓力遠程監測系統。現場儀表使用高精度電橋采集數據，通過433 MHz短距離無線通信網絡與遠程終端RTU進行通信，RTU通過GPRS網絡與PC上位機進行遠程數據傳輸，在上位機中實現數據存儲和圖形化界面顯示，從而實現輸油管道溫度壓力參數的實時監測和異常報警。經實驗證明，該系統的12位數據采集精度滿足設計要求，漏碼率小于1%，正常工作時間超過5個月，能實時有效地監測輸油管道的溫度壓力參數，節省大量人工成本，有效預防管道參數異常造成的經濟損失和環境污染。 Abstract: In order to solve the problems on real-time monitoring of pipeline temperature and pressure parameters， the ultra-low power remote pipeline temperature and pressure monitoring system was designed by using the single chip processor C8051F930 as the control core. The high-precision electric bridge was used in field instruments for data collection， the 433MHz short-range wireless communication network was used to make communication between field instrument and RTU， the GPRS was used by the RTU to transmit data to the PC host computer， and the data was stored and displayed in the PC host computer， so the real-time monitoring and exception alerts of pipeline temperature and pressure parameters were achieved. The experiment proves that the system of which error rate is less than 1% over five months working with the 12-bit data acquisition accuracy can effectively monitor the pipeline temperature and pressure parameters in real time， it saves a lot of labor costs and effectively prevents environmental pollution and economic losses caused by abnormal channel parameters.
上傳時間： 2013-11-07
上傳用戶：cuibaigao
The PCA9516 is a BiCMOS integrated circuit intended forapplication in I2C and SMBus systems.While retaining all the operating modes and features of the I2Csystem, it permits extension of the I2C-bus by buffering both the data(SDA) and the clock (SCL) lines, thus enabling five buses of 400 pF.The I2C-bus capacitance limit of 400 pF restricts the number ofdevices and bus length. Using the PCA9516 enables the systemdesigner to divide the bus into five segments off of a hub where anysegment to segment transition sees only one repeater delay.
上傳時間： 2013-11-21
上傳用戶：q123321
The MAX3243E device consists of three line drivers, five line receivers, and a dual charge-pump circuit with±15-kV ESD (HBM and IEC61000-4-2, Air-Gap Discharge) and ±8-kV ESD (IEC61000-4-2, Contact Discharge)protection on serial-port connection pins. The device meets the requirements of TIA/EIA-232-F and provides theelectrical interface between an asynchronous communication controller and the serial-port connector. Thiscombination of drivers and receivers matches that needed for the typical serial port used in an IBM PC/AT, orcompatible. The charge pump and four small external capacitors allow operation from a single 3-V to 5.5-Vsupply. In addition, the device includes an always-active noninverting output (ROUT2B), which allowsapplications using the ring indicator to transmit data while the device is powered down. The device operates atdata signaling rates up to 250 kbit/s and a maximum of 30-V/ms driver output slew rate.
標簽： MULTICHANNEL 5.5 TO RS
上傳時間： 2013-10-19
上傳用戶：ddddddd
This application note covers the design considerations of a system using the performance features of the LogiCORE™ IP Advanced eXtensible Interface (AXI) Interconnect core. The design focuses on high system throughput through the AXI Interconnect core with F MAX and area optimizations in certain portions of the design. The design uses five AXI video direct memory access (VDMA) engines to simultaneously move 10 streams (five transmit video streams and five receive video streams), each in 1920 x 1080p format, 60 Hz refresh rate, and up to 32 data bits per pixel. Each VDMA is driven from a video test pattern generator (TPG) with a video timing controller (VTC) block to set up the necessary video timing signals. Data read by each AXI VDMA is sent to a common on-screen display (OSD) core capable of multiplexing or overlaying multiple video streams to a single output video stream. The output of the OSD core drives the DVI video display interface on the board. Performance monitor blocks are added to capture performance data. All 10 video streams moved by the AXI VDMA blocks are buffered through a shared DDR3 SDRAM memory and are controlled by a MicroBlaze™ processor. The reference system is targeted for the Virtex-6 XC6VLX240TFF1156-1 FPGA on the Xilinx® ML605 Rev D evaluation board
上傳時間： 2013-11-14
上傳用戶：fdmpy
This application note covers the design considerations of a system using the performance features of the LogiCORE™ IP Advanced eXtensible Interface (AXI) Interconnect core. The design focuses on high system throughput through the AXI Interconnect core with F MAX and area optimizations in certain portions of the design. The design uses five AXI video direct memory access (VDMA) engines to simultaneously move 10 streams (five transmit video streams and five receive video streams), each in 1920 x 1080p format, 60 Hz refresh rate, and up to 32 data bits per pixel. Each VDMA is driven from a video test pattern generator (TPG) with a video timing controller (VTC) block to set up the necessary video timing signals. Data read by each AXI VDMA is sent to a common on-screen display (OSD) core capable of multiplexing or overlaying multiple video streams to a single output video stream. The output of the OSD core drives the DVI video display interface on the board. Performance monitor blocks are added to capture performance data. All 10 video streams moved by the AXI VDMA blocks are buffered through a shared DDR3 SDRAM memory and are controlled by a MicroBlaze™ processor. The reference system is targeted for the Virtex-6 XC6VLX240TFF1156-1 FPGA on the Xilinx® ML605 Rev D evaluation board
上傳時間： 2013-11-23
上傳用戶：shen_dafa
This program demonstrates using watchdog timers to invoke deadline handlers. CoordinatorTask sends data to the organizer. OrganizerTask receives data from the coordinatorTask, and resets the coordinatorTask when no data is sent by the coordinatorTask in the past five seconds (deadline time). This demonstration program is automatically stopped after twenty seconds.
標簽： CoordinatorTask demonstrates deadline handlers
上傳時間： 2015-09-21
上傳用戶：大融融rr
