AT89C2051驅動步進電機的電路和源碼:AT89C2051驅動步進電機的電路和源碼 程序:stepper.c stepper.hex/* * STEPPER.C * sweeping stepper's rotor cw and cww 400 steps * Copyright (c) 1999 by W.Sirichote */＃i nclude c:\mc5151io.h /* include i/o header file */ ＃i nclude c:\mc5151reg.hregister unsigned char j,flag1,temp; register unsigned int cw_n,ccw_n;unsigned char step[8]={0x80,0xc0,0x40,0x60,0x20,0x30,0x10,0x90} #define n 400/* flag1 mask byte 0x01 run cw() 0x02 run ccw() */main(){ flag1=0; serinit(9600); disable(); /* no need timer interrupt */ cw_n = n; /* initial step number for cw */ flag1 |=0x01; /* initial enable cw() */while(1){ { tick_wait(); /* wait for 10ms elapsed */energize(); /* round-robin execution the following tasks every 10ms */ cw(); ccw(); } }}cw(){ if((flag1&0x01)!=0) { cw_n--; /* decrement cw step number */ if (cw_n !=0) j++; /* if not zero increment index j */ else {flag1&=~0x01; /* disable cw() execution */ ccw_n = n; /* reload step number to ccw counter */ flag1 |=0x02; /* enable cww() execution */ } }
標簽：
C2051
2051
89C
AT
上傳時間：
2013-11-21
上傳用戶：boyaboy
The Motorola MPC106 PCI bridge/memory controller provides a PowerPCªmicroprocessor common hardware reference platform (CHRPª) compliant bridgebetween the PowerPC microprocessor family and the Peripheral Component Interconnect(PCI) bus. In this document, the term Ô106Õ is used as an abbreviation for the phraseÔMPC106 PCI bridge/memory controllerÕ. This document contains pertinent physicalcharacteristics of the 106. For functional characteristics refer to theMPC106 PCI Bridge/Memory Controller UserÕs Manual.This document contains the following topics:Topic PageSection 1.1, ÒOverviewÓ 2Section 1.2, ÒFeaturesÓ 3Section 1.3, ÒGeneral ParametersÓ 5Section 1.4, ÒElectrical and Thermal CharacteristicsÓ 5Section 1.5, ÒPin AssignmentsÓ 17Section 1.6, ÒPinout Listings 18Section 1.7, ÒPackage DescriptionÓ 22Section 1.8, ÒSystem Design InformationÓ 24Section 1.9, ÒDocument Revision HistoryÓ 29Section 1.10, ÒOrdering InformationÓ 29
標簽：
MPC
106
PCI
存儲器
上傳時間：
2013-11-04
上傳用戶：as275944189
The LogiCORE™ GTP Wizard automates the task of creating HDL wrappers to configure the high-speed serial GTP transceivers in Virtex™-5 LXT and SXT devices. The menu-driven interface allows one or more GTP transceivers to be configured using pre-definedtemplates for popular industry standards, or from scratch, to support a wide variety of custom protocols.The Wizard produces a wrapper, an example design, and a testbench for rapid integration and verification of the serial interface with your custom function
Features• Creates customized HDL wrappers to configureVirtex-5 RocketIO™ GTP transceivers• Users can configure Virtex-5 GTP transceivers toconform to industry standard protocols usingpredefined templates, or tailor the templates forcustom protocols• Included protocol templates provide support for thefollowing specifications: Aurora, CPRI, FibreChannel 1x, Gigabit Ethernet, HD-SDI, OBSAI,OC3, OC12, OC48, PCI Express® (PCIe®), SATA,SATA II, and XAUI• Automatically configures analog settings• Each custom wrapper includes example design, testbench; and both implementation and simulation scripts
標簽：
Transceiver
Virtex
Wizar
GTP
上傳時間：
2013-10-23
上傳用戶：leyesome
