針對(duì)當(dāng)前安檢力學(xué)試驗(yàn)機(jī)所能完成的試驗(yàn)種類單一、自動(dòng)化程度低等問題，提出一種以ATmega128單片機(jī)為核心控制器的安檢力學(xué)試驗(yàn)機(jī)的設(shè)計(jì)。詳細(xì)闡述了該安檢力學(xué)試驗(yàn)機(jī)各個(gè)組成部分的設(shè)計(jì)原理和方案，并且給出了各部分的軟件設(shè)計(jì)思想和操作流程。經(jīng)過大量測試試驗(yàn)表明：設(shè)計(jì)的安檢力學(xué)試驗(yàn)機(jī)可以完成多達(dá)十余種的力學(xué)安檢試驗(yàn)，完全符合相關(guān)國家標(biāo)準(zhǔn)，并且具有數(shù)據(jù)采集精度高、傳輸速度快、操作安全簡便等特點(diǎn)，實(shí)現(xiàn)了安檢設(shè)備的多功能化、數(shù)字化和自動(dòng)化。 Abstract: Currently， many mechanical security testing machines have only one function. The degree of automation of them is low. To solve those problems， a new kind of mechanical security testing machine， using ATmega128 micro-controller as its core controller， has been advanced. It describes the components of the machine. The principles and the scheme in the designing processes are presented in detail， and the software architecture and the operation processes of each part are given. After having done many testing， we have reached the following conclusions: the mechanical security testing machine presented can do over ten mechanical security tests complying with related national standards. It has high data acquisition accuracy and high transmission speed. The operation of the machine is simple and safe. In general， this machine is a multi-functional， highly automatic， digitalized security testing device.
標(biāo)簽： ATmega 128 安檢 試驗(yàn)機(jī)
上傳時(shí)間： 2013-11-05
上傳用戶：a67818601
dsPIC30F產(chǎn)品手冊(cè) High Performance Digital Signal Controllers This section of the manual contains the following topics:1.1 Introduction 1.2 Manual Objective 1.3 Device Structure1.4 Development Support 1.5 Style and Symbol Conventions 1.6 Related Documents 1.7 Revision History
標(biāo)簽： dsPIC 30F 30 產(chǎn)品手冊(cè)
上傳時(shí)間： 2013-12-26
上傳用戶：xzt
FeaturesThe following standard features are provided.• Choice of RTOS scheduling policy1. Pre-emptive:Always runs the highest available task. Tasks of identical priorityshare CPU time (fully pre-emptive with round robin time slicing).2. Cooperative:Context switches only occur if a task blocks, or explicitly callstaskYIELD().• Co-routines (light weight tasks that utilise very little RAM).• Message queues• Semaphores [via macros]• Trace visualisation ability (requires more RAM)• Majority of source code common to all supported development tools• Wide range of ports and examples
上傳時(shí)間： 2013-10-13
上傳用戶：13162218709
AT89C2051驅(qū)動(dòng)步進(jìn)電機(jī)的電路和源碼:AT89C2051驅(qū)動(dòng)步進(jìn)電機(jī)的電路和源碼 程序:stepper.c stepper.hex/* * STEPPER.C * sweeping stepper's rotor cw and cww 400 steps * Copyright (c) 1999 by W.Sirichote */＃i nclude c:\mc5151io.h /* include i/o header file */ ＃i nclude c:\mc5151reg.hregister unsigned char j,flag1,temp; register unsigned int cw_n,ccw_n;unsigned char step[8]={0x80,0xc0,0x40,0x60,0x20,0x30,0x10,0x90} #define n 400/* flag1 mask byte 0x01 run cw() 0x02 run ccw() */main(){ flag1=0; serinit(9600); disable(); /* no need timer interrupt */ cw_n = n; /* initial step number for cw */ flag1 |=0x01; /* initial enable cw() */while(1){ { tick_wait(); /* wait for 10ms elapsed */energize(); /* round-robin execution the following tasks every 10ms */ cw(); ccw(); } }}cw(){ if((flag1&0x01)!=0) { cw_n--; /* decrement cw step number */ if (cw_n !=0) j++; /* if not zero increment index j */ else {flag1&=~0x01; /* disable cw() execution */ ccw_n = n; /* reload step number to ccw counter */ flag1 |=0x02; /* enable cww() execution */ } }
上傳時(shí)間： 2013-11-21
上傳用戶：boyaboy
The Motorola MPC106 PCI bridge/memory controller provides a PowerPCªmicroprocessor common hardware reference platform (CHRPª) compliant bridgebetween the PowerPC microprocessor family and the Peripheral Component Interconnect(PCI) bus. In this document, the term Ô106Õ is used as an abbreviation for the phraseÔMPC106 PCI bridge/memory controllerÕ. This document contains pertinent physicalcharacteristics of the 106. For functional characteristics refer to theMPC106 PCI Bridge/Memory Controller UserÕs Manual.This document contains the following topics:Topic PageSection 1.1, ÒOverviewÓ 2Section 1.2, ÒFeaturesÓ 3Section 1.3, ÒGeneral ParametersÓ 5Section 1.4, ÒElectrical and Thermal CharacteristicsÓ 5Section 1.5, ÒPin AssignmentsÓ 17Section 1.6, ÒPinout Listings 18Section 1.7, ÒPackage DescriptionÓ 22Section 1.8, ÒSystem Design InformationÓ 24Section 1.9, ÒDocument Revision HistoryÓ 29Section 1.10, ÒOrdering InformationÓ 29
標(biāo)簽： MPC 106 PCI 存儲(chǔ)器
上傳時(shí)間： 2013-11-04
上傳用戶：as275944189
The 87C576 includes two separate methods of programming theEPROM array, the traditional modified Quick-Pulse method, and anew On-Board Programming technique (OBP).Quick Pulse programming is a method using a number of devicepins in parallel (see Figure 1) and is the traditional way in which87C51 family members have been programmed. The Quick-Pulsemethod supports the following programming functions:– program USER EPROM– verify USER EPROM– program KEY EPROM– program security bits– verify security bits– read signature bytesThe Quick-Pulse method is quite easily suited to standardprogramming equipment as evidenced by the numerous vendors of87C51 compatible programmers on the market today. Onedisadvantage is that this method is not well suited to programming inthe embedded application because of the large number of signallines that must be isolated from the application. In addition, parallelsignals from a programmer would need to be cabled to theapplication’s circuit board, or the application circuit board wouldneed to have logic built-in to perform the programming functions.These requirements have generally made in-circuit programmingusing the modified Quick Pulse method impractical in almost all87C51 family applications.
上傳時(shí)間： 2013-10-21
上傳用戶：xiaozhiqban
The LogiCORE™ GTP Wizard automates the task of creating HDL wrappers to configure the high-speed serial GTP transceivers in Virtex™-5 LXT and SXT devices. The menu-driven interface allows one or more GTP transceivers to be configured using pre-definedtemplates for popular industry standards, or from scratch, to support a wide variety of custom protocols.The Wizard produces a wrapper, an example design, and a testbench for rapid integration and verification of the serial interface with your custom function Features• Creates customized HDL wrappers to configureVirtex-5 RocketIO™ GTP transceivers• Users can configure Virtex-5 GTP transceivers toconform to industry standard protocols usingpredefined templates, or tailor the templates forcustom protocols• Included protocol templates provide support for thefollowing specifications: Aurora, CPRI, FibreChannel 1x, Gigabit Ethernet, HD-SDI, OBSAI,OC3, OC12, OC48, PCI Express® (PCIe®), SATA,SATA II, and XAUI• Automatically configures analog settings• Each custom wrapper includes example design, testbench; and both implementation and simulation scripts
標(biāo)簽： Transceiver Virtex Wizar GTP
上傳時(shí)間： 2013-10-23
上傳用戶：leyesome
ZBT SRAM控制器參考設(shè)計(jì),xilinx提供VHDL代碼 Description: Contains the following files readme.txt appnote_zbtp.vhd appnote_zbtf.vhd appnote_zbt.ucf Platform: All Installation/Use: Use 'unzip' on the .zip file and 'gunzip' followed by 'tar -xvf' on the .tar.gz file.
標(biāo)簽： xilinx SRAM VHDL ZBT
上傳時(shí)間： 2013-11-24
上傳用戶：31633073
UART 4 UART參考設(shè)計(jì)，Xilinx提供VHDL代碼 uart_vhdl This zip file contains the following folders: \vhdl_source -- Source VHDL files: uart.vhd - top level file txmit.vhd - transmit portion of uart rcvr.vhd - - receive portion of uart \vhdl_testfixture -- VHDL Testbench files. This files only include the testbench behavior, they do not instantiate the DUT. This can easily be done in a top-level VHDL file or a schematic. This folder contains the following files: txmit_tb.vhd -- Test bench for txmit.vhd. rcvr_tf.vhd -- Test bench for rcvr.vhd.
標(biāo)簽： UART Xilinx VHDL 參考設(shè)計(jì)
上傳時(shí)間： 2013-11-07
上傳用戶：jasson5678
You can use the ByteBlasterMV? download cable to do the following:
標(biāo)簽： ALTERA 編程電纜 數(shù)據(jù)手冊(cè)
上傳時(shí)間： 2013-10-10
上傳用戶：上善若水
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