1、 支持USB 1.1通訊協(xié)議；2、 支持高速（Full Speed、12Mbps ）和低速（Low Speed、1.5Mbps ）傳輸；3、 6MHz晶體，鎖相環(huán)PLL振蕩器提供高速、低速所需時鐘源；4、 支持3個端口（endpoint），可獨(dú)立編程為IN 或 OUT端口。5、 PS/2：支持PS/2協(xié)議（eg.鼠標(biāo)），與USB復(fù)用。
上傳時間： 2013-11-03
上傳用戶：hbsunhui
<Almost since the introduction of microcontrollers as electronic components there always has been an oscillatorcircuit on the device to make it work. From application point of view only some external components wererequired to make it work. However, to make sure that it will always work required more effort. This report is basedon feedback from the market from customers applying 8-bit mircrocontrollers.>
標(biāo)簽： oscillators X-tal bit mic
上傳時間： 2013-11-12
上傳用戶：穿著衣服的大衛(wèi)
The PCA9544A provides 4 interrupt inputs, one for each channeland one open drain interrupt output. When an interrupt is generated byany device, it will be detected by the PCA9544A and the interruptoutput will be driven LOW. The channel need not be active fordetection of the interrupt. A bit is also set in the control byte.Bits 4 – 7 of the control byte correspond to channels 0 – 3 of thePCA9544A, respectively. Therefore, if an interrupt is generated byany device connected to channel 2, the state of the interrupt inputs isloaded into the control register when a read is accomplished.Likewise, an interrupt on any device connected to channel 0 wouldcause bit 4 of the control register to be set on the read. The mastercan then address the PCA9544A and read the contents of thecontrol byte to determine which channel contains the devicegenerating the interrupt. The master can then reconfigure thePCA9544A to select this channel, and locate the device generatingthe interrupt and clear it. The interrupt clears when the deviceoriginating the interrupt clears.
標(biāo)簽： 4channel multiple 9544A 9544
上傳時間： 2014-12-28
上傳用戶：潛水的三貢
The PCA9549 provides eight bits of high speed TTL-compatible bus switching controlledby the I2C-bus. The low ON-state resistance of the switch allows connections to be madewith minimal propagation delay. Any individual A to B channel or combination of channelscan be selected via the I2C-bus, determined by the contents of the programmable Controlregister. When the I2C-bus bit is HIGH (logic 1), the switch is on and data can flow fromPort A to Port B, or vice versa. When the I2C-bus bit is LOW (logic 0), the switch is open,creating a high-impedance state between the two ports, which stops the data flow.An active LOW reset input (RESET) allows the PCA9549 to recover from a situationwhere the I2C-bus is stuck in a LOW state. Pulling the RESET pin LOW resets the I2C-busstate machine and causes all the bits to be open, as does the internal power-on resetfunction.
標(biāo)簽： switch Octal 9549 with
上傳時間： 2014-11-22
上傳用戶：xcy122677
The PCA9548A is an octal bidirectional translating switch controlled via the I2C-bus. TheSCL/SDA upstream pair fans out to eight downstream pairs, or channels. Any individualSCx/SDx channel or combination of channels can be selected, determined by thecontents of the programmable control register.An active LOW reset input allows the PCA9548A to recover from a situation where one ofthe downstream I2C-buses is stuck in a LOW state. Pulling the RESET pin LOW resets theI2C-bus state machine and causes all the channels to be deselected as does the internalPower-on reset function.
標(biāo)簽： channel 9548A 9548 PCA
上傳時間： 2013-10-13
上傳用戶：bakdesec
The PCA9557 is a silicon CMOS circuit which provides parallel input/output expansion for SMBus and I2C-bus applications. The PCA9557 consists of an 8-bit input port register, 8-bit output port register, and an I2C-bus/SMBus interface. It has low current consumption and a high-impedance open-drain output pin, IO0. The system master can enable the PCA9557’s I/O as either input or output by writing to the configuration register. The system master can also invert the PCA9557 inputs by writing to the active HIGH polarity inversion register. Finally, the system master can reset the PCA9557 in the event of a time-out by asserting a LOW in the reset input. The power-on reset puts the registers in their default state and initializes the I2C-bus/SMBus state machine. The RESET pin causes the same reset/initialization to occur without de-powering the part.
標(biāo)簽： C-bus SMBus reset port
上傳時間： 2014-01-18
上傳用戶：bs2005
KEIL RTX51實(shí)時操作系統(tǒng)中文版:RTX51是一個適用于8051 家族的實(shí)時多任務(wù)操作系統(tǒng)。RTX51使復(fù)雜的系統(tǒng)和軟件設(shè)計(jì)以及有時間限制的工程開發(fā)變得簡單。RTX51是一個強(qiáng)大的工具，它可以在單個CPU上管理幾個作業(yè)（任務(wù)）。RTX51有兩種不同的版本。 RTX51 Full 允許4個優(yōu)先權(quán)任務(wù)的循環(huán)和切換，并且還能并行的利用中斷功能。RTX51 支持信號傳遞，以及與系統(tǒng)郵箱和信號量進(jìn)行消息傳遞。RTX51的os_wait 函數(shù)可以等以 下事件：中斷、時間到、來自任務(wù)或中斷的信號、來自任務(wù)或中斷的消息、信號量。 RTX51 Tiny 是RTX51 Full 的一個子集。RTX51 Tiny 可以很容易的運(yùn)行在沒有擴(kuò)展外 部存儲器的單片機(jī)系統(tǒng)上。但是，使用RTX51 Tiny 的程序可以訪問外部存儲器。RTX51 Tiny允許循環(huán)任務(wù)切換，并且支持信號傳遞，還能并行的利用中斷功能。RTX51 Tiny 的os_wait函數(shù)可以等待以下事件：時間到、時間間隔、來自任務(wù)或者中斷的信號。 本章節(jié)以后的部分用RTX-51 來指代RTX-51 Full 和RTX-51 Tiny。在兩者之間不同的 地方會加以說明。
標(biāo)簽： KEIL RTX 51 實(shí)時操作系統(tǒng)
上傳時間： 2013-11-25
上傳用戶：axin881314
設(shè)計(jì)一種應(yīng)用于某全地形ATV車載武器裝置中的中控系統(tǒng)，該系統(tǒng)設(shè)計(jì)是以TMS320F2812型DSP為核心，采用模塊化設(shè)計(jì)思想，對其硬件部分進(jìn)行系統(tǒng)設(shè)計(jì)，能夠完成對武器裝置高低、回轉(zhuǎn)方向的運(yùn)動控制，實(shí)現(xiàn)靜止或行進(jìn)狀態(tài)中對目標(biāo)物的測距，自動瞄準(zhǔn)以及按既定發(fā)射模式發(fā)射彈丸和各項(xiàng)安全性能檢測等功能。通過編制相應(yīng)的軟件，對其進(jìn)行系統(tǒng)調(diào)試，驗(yàn)證了該設(shè)計(jì)運(yùn)行穩(wěn)定。 Abstract: A central control system applied to an ATV vehicle weapons is designed. The system design is based on TMS320F2812 DSP as the core， uses modular design for its hardware parts. The central control system can complete the motion control of the level of weapons and equipment， rotation direction， to achieve a state of static or moving objects on the target ranging， auto-targeting and according to the established target and the projectile and the launch of the security performance testing and other functions. Through the development of appropriate software and to carry out system testing to verify the stability of this design and operation.
標(biāo)簽： ATV-ATT DSP 中控系統(tǒng)
上傳時間： 2013-11-02
上傳用戶：jshailingzzh
This application note describes how to build a system that can be used for determining theoptimal phase shift for a Double Data Rate (DDR) memory feedback clock. In this system, theDDR memory is controlled by a controller that attaches to either the OPB or PLB and is used inan embedded microprocessor application. This reference system also uses a DCM that isconfigured so that the phase of its output clock can be changed while the system is running anda GPIO core that controls that phase shift. The GPIO output is controlled by a softwareapplication that can be run on a PowerPC® 405 or Microblaze™ microprocessor.
上傳時間： 2013-10-15
上傳用戶：euroford
WP369可擴(kuò)展式處理平臺-各種嵌入式系統(tǒng)的理想解決方案 ：Delivering unrivaled levels of system performance,flexibility, scalability, and integration to developers,Xilinx's architecture for a new Extensible Processing Platform is optimized for system power, cost, and size. Based on ARM's dual-core Cortex™-A9 MPCore processors and Xilinx’s 28 nm programmable logic,the Extensible Processing Platform takes a processor-centric approach by defining a comprehensive processor system implemented with standard design methods. This approach provides Software Developers a familiar programming environment within an optimized, full featured,powerful, yet low-cost, low-power processing platform.
標(biāo)簽： 369 WP 擴(kuò)展式 處理平臺
上傳時間： 2013-10-22
上傳用戶：685
蟲蟲下載站版權(quán)所有 京ICP備2021023401號-1
