FPGA片內FIFO讀寫測試Verilog邏輯源碼Quartus工程文件+文檔說明，使用 FPGA 內部的 FIFO 以及程序對該 FIFO 的數據讀寫操作。FPGA型號Cyclone4E系列中的EP4CE6F17C8，Quartus版本17.1。timescale 1ns / 1ps//////////////////////////////////////////////////////////////////////////////////module fifo_test( input clk, //50MHz時鐘 input rst_n //復位信號，低電平有效 );//-----------------------------------------------------------localparam W_IDLE = 1;localparam W_FIFO = 2; localparam R_IDLE = 1;localparam R_FIFO = 2; reg[2:0] write_state;reg[2:0] next_write_state;reg[2:0] read_state;reg[2:0] next_read_state;reg[15:0] w_data; //FIFO寫數據wire wr_en; //FIFO寫使能wire rd_en; //FIFO讀使能wire[15:0] r_data; //FIFO讀數據wire full; //FIFO滿信號 wire empty; //FIFO空信號 wire[8:0] rd_data_count; wire[8:0] wr_data_count; ///產生FIFO寫入的數據always@(posedge clk or negedge rst_n)begin if(rst_n == 1'b0) write_state <= W_IDLE; else write_state <= next_write_state;endalways@(*)begin case(write_state) W_IDLE: if(empty == 1'b1) //FIFO空， 開始寫FIFO next_write_state <= W_FIFO; else next_write_state <= W_IDLE; W_FIFO: if(full == 1'b1) //FIFO滿 next_write_state <= W_IDLE; else next_write_state <= W_FIFO; default: next_write_state <= W_IDLE; endcaseendassign wr_en = (next_write_state == W_FIFO) ? 1'b1 : 1'b0; always@(posedge clk or negedge rst_n)begin if(rst_n == 1'b0) w_data <= 16'd0; else if (wr_en == 1'b1) w_data <= w_data + 1'b1; else w_data <= 16'd0; end///產生FIFO讀的數據always@(posedge clk or negedge rst_n)begin if(rst_n == 1'b0) read_state <= R_IDLE; else read_state <= next_read_state;endalways@(*)begin case(read_state) R_IDLE: if(full == 1'b1) //FIFO滿, 開始讀FIFO next_read_state <= R_FIFO; else next_read_state <= R_IDLE; R_FIFO: if(empty == 1'b1)
上傳時間： 2021-12-19
上傳用戶：20125101110
1. Scope ......................................................................................................................................................................... 12. DDR4 SDRAM Package Pinout and Addressing ....................................................................................................... 22.1 DDR4 SDRAM Row for X4,X8 and X16 ................................................................................................................22.2 DDR4 SDRAM Ball Pitch........................................................................................................................................22.3 DDR4 SDRAM Columns for X4,X8 and X16 ..........................................................................................................22.4 DDR4 SDRAM X4/8 Ballout using MO-207......................................................................................................... 22.5 DDR4 SDRAM X16 Ballout using MO-207.............................................................................................................32.6 Pinout Description ..................................................................................................................................................52.7 DDR4 SDRAM Addressing.....................................................................................................................................73. Functional Description ...............................................................................................................................................83.1 Simplified State Diagram ....................................................................................................................................83.2 Basic Functionality..................................................................................................................................................93.3 RESET and Initialization Procedure .....................................................................................................................103.3.1 Power-up Initialization Sequence .............................................................................................................103.3.2 Reset Initialization with Stable Power ......................................................................................................113.4 Register Definition ................................................................................................................................................123.4.1 Programming the mode registers .............................................................................................................123.5 Mode Register ......................................................................................................................................................134. DDR4 SDRAM Command Description and Operation ............................................................................................. 244.1 Command Truth Table ..........................................................................................................................................244.2 CKE Truth Table ...................................................................................................................................................254.3 Burst Length, Type and Order ..............................................................................................................................264.3.1 BL8 Burst order with CRC Enabled .........................................................................................................264.4 DLL-off Mode & DLL on/off Switching procedure ................................................................................................274.4.1 DLL on/off switching procedure ...............................................................................................................274.4.2 DLL “on” to DLL “off” Procedure ..............................................................................................................274.4.3 DLL “off” to DLL “on” Procedure ..............................................................................................................284.5 DLL-off Mode........................................................................................................................................................294.6 Input Clock Frequency Change ............................................................................................................................304.7 Write Leveling.......................................................................................................................................................314.7.1 DRAM setting for write leveling & DRAM termination function in that mode ............................................324.7.2 Procedure Description .............................................................................................................................334.7.3 Write Leveling Mode Exit .........................................................................................................................34
標簽： DDR4
上傳時間： 2022-01-09
上傳用戶：
Keil激活_Keygen-Decompressed-Full-2030.zip
標簽： Keil
上傳時間： 2022-01-28
上傳用戶：
The PW3130 series product is a high integration solution for lithium-lion/polymer batteryprotection.PW3130 contains advanced power MOSFET, high-accuracy voltage detection circuits anddelay circuits. PW3130 is put into an ultra-small SOT23-5 package and only one external componentmakes it an ideal solution in limited space of battery pack. PW3130 has all the protection functionsrequired in the battery application including overcharging, overdischarging, overcurrent and loadshort circuiting protection etc. The accurate overcharging detection voltage ensures safe and fullutilization charging.The low standby current drains little current from the cell while in storage. Thedevice is not only targeted for digital cellular phones, but also for any other Li-Ion and Li-Polybattery-powered information appliances requiring long-term battery life
標簽： pw3130
上傳時間： 2022-02-11
上傳用戶：fliang
InGaAs/AlGaAs semiconductor lasers come in threetypes: VCSELs and two types of EELs. The VCSEL, asits name implies, emits vertically, normal to the planeof the device, owing to cavity mirrors grown withinthe epitaxial material itself. The VCSEL’s circular beamhas a numerical aperture (NA) of roughly 0.2, or a fullangle of approximately 25 degrees.
標簽： tof
上傳時間： 2022-02-12
上傳用戶：
本書是 Marc Thompson 博士 20 年模擬電路設計和教學經驗的總結，講述了模擬電路與系統設計中常用的直觀分析方法。本書提出了“模擬電路直觀方法學”，力圖幫助學生和設計人員擺脫復雜的理論推導與計算，充分利用直觀知識來應對模擬電路工程設計挑戰。全書共分為 16 章，內容涵蓋了二極管、晶體管、放大器、濾波器、反饋系統等模擬電路的基本知識與設計方法。本書大綱第 1 章與第 2 章為介紹性材料。第 1 章是本書的引言，同時介紹了模擬電路設計的發展動機，其中引用了一些精選的歷史事件。第 2 章講述后續章節中用到地重要的信號處理概念，以使讀者們能夠跟上作者的思路。第 3 章至第 8 章講述雙極性器件的物理學原理、雙極性結型晶體管 (bipolar junction transistor, BJT) 、晶體管放大器，以及用于帶寬估計與開關速度分析的近似技術。第 9 章講述 CMOS 管和 CMOS 管放大器的基礎知識。前面章節介紹的用于放大器設計的帶寬估計技術也同樣適用于 CMOS 管器件。第 10 章講述 晶體管的開關效應。晶體管是如何實現導通和關閉呢？又如何估計它的開關速度呢？第 11 章回顧反饋系統 (feedback system) 的基本知識以及設計穩定反饋系統的伯德圖 / 相位裕度方法 (Bod plot / phase margin) 。第 12 章和第 13 章講述實際運算放大器的設計、使用和限制，包括電壓反饋 (voltage-feedback) 以及電流反饋 (current-feedback) 放大器。第 14 章講述模擬低通濾波器設計的基本知識，包括巴特沃思 (Butterworth) 、切比雪夫 (Chebyshev) 、橢圓 (elliptic) 以及貝塞爾 (Bessel) 濾波器的無源梯形實現和胡源實現。第 15 章講述實際電路設計問題，比如 PCB 版圖設計規則、無源器件的使用和限制等。第 16 章是一些有用的設計技術和設計技巧的大雜燴，這些內容又不適合放在其他章節，所以作為獨立的章節進行講述。一些說明性的分析問題以及 MATLAB 和 SPICE 設計示例點綴在全書的字里行間，以幫助讀者理解本書的內容。
標簽： 模擬電路
上傳時間： 2022-02-14
上傳用戶：
The PW2053 is a high-efficiency monolithic synchronous buck regulator using a constantfrequency, current mode architecture. The device is available in an adjustable version. Supply currentwith no load is 40uA and drops to <1uA in shutdown. The 2.5V to 5.5V input voltage range makesthe PW2053 ideally suited for single Li-Ion battery powered applications. 100% duty cycle provideslow dropout operation, extending battery life in portable systems. PWM/PFM mode operationprovides very low output ripple voltage for noise sensitive applications. Switching frequency isinternally set at 1.2MHz, allowing the use of small surface mount inductors and capacitors. Lowoutput voltages are easily supported with the 0.6V feedback reference voltage
標簽： pw2053
上傳時間： 2022-02-14
上傳用戶：jason_vip1
The PW8205A8TS is the highest performance trench N-ch MOSFETs with extreme high cell density,which provide excellent RDSON and gate charge for most of the small power switching and loadswitch applications. The meet the RoHS and Product requirement with full function reliabilityapproved .
標簽： 8205a8
上傳時間： 2022-02-14
上傳用戶：wangshoupeng199
Single chip TFT-LCD Controller/Driver with On-chip Frame Memory (FM) Display Resolution: 240*RGB (H) *320(V) Frame Memory Size: 240 x 320 x 18-bit = 1,382,400 bits LCD Driver Output Circuits- Source Outputs: 240 RGB Channels- Gate Outputs: 320 Channels- Common Electrode Output Display Colors (Color Mode)- Full Color: 262K, RGB=(666) max., Idle Mode Off- Color Reduce: 8-color, RGB=(111), Idle Mode On Programmable Pixel Color Format (Color Depth) for Various Display Data input Format- 12-bit/pixel: RGB=(444)- 16-bit/pixel: RGB=(565)- 18-bit/pixel: RGB=(666) MCU Interface- Parallel 8080-series MCU Interface (8-bit, 9-bit, 16-bit & 18-bit)- 6/16/18 RGB Interface(VSYNC, HSYNC, DOTCLK, ENABLE, DB[17:0])- Serial Peripheral Interface(SPI Interface)- VSYNC Interface
上傳時間： 2022-03-04
上傳用戶：
目前電動汽車主要以鋰電池作為動力來源,為了提高鋰電池的使用時間和安全性,為鋰電池提供安全良好的運行環境,電池管理系統應運而生。BMS主控單元基于S32K144汽車級單片機,通過主從式網絡控制結構能夠對鋰電池的各個參數進行采集與分析。采用擴展卡爾曼濾波對電池的荷電狀態(SOC)進行估算,克服普通估算方法無法避免電池內阻誤差的缺點,通過Matlab/Simulink軟件仿真驗證可使估算誤差達到2%以內。At present,electric vehicles mainly use lithium batteries as the power source.In order to improve the running time and safety of lithium batteries,a safe and good operating environment for power batteries is provided,and a battery management system(BMS) has emerged.The BMS main control unit is based on the S32K144 automotive-grade control chip.Through the master-slave network control structure,it can collect and analyze the various parameters of the lithium battery.The Extended Kalman Filter(EKF) is used to estimate the state of charge(SOC) of the battery,which overcomes the shortcomings of the internal estimation method that cannot overcome the internal resistance error of the battery.It can be verified by Matlab/Simulink software simulation.The estimation error is within 2%.
上傳時間： 2022-03-26
上傳用戶：XuVshu
