With the Altera Nios II embedded processor, you as the system designercan accelerate time-critical software algorithms by adding custominstructions to the Nios II processor instruction set. Using custominstructions, you can reduce a complex sequence of standard instructionsto a single instruction implemented in hardware. You can use this featurefor a variety of applications, for example, to optimize software innerloops for digital signal processing (DSP), packet header processing, andcomputation-intensive applications. The Nios II configuration wizard,part of the Quartus® II software’s SOPC Builder, provides a graphicaluser interface (GUI) used to add up to 256 custom instructions to theNios II processor
通過比較各種隔離數(shù)字通信的特點(diǎn)和應(yīng)用范圍，指出塑料光纖在隔離數(shù)字通信中的優(yōu)勢。使用已經(jīng)標(biāo)準(zhǔn)化的TOSLINK接口，有利于節(jié)省硬件開發(fā)成本和簡化設(shè)計(jì)難度。給出了塑料光纖的硬件驅(qū)動電路，說明設(shè)計(jì)過程中的注意事項(xiàng)，對光收發(fā)模塊的電壓特性和頻率特性進(jìn)行全面試驗(yàn)，并給出SPI口使用塑料光纖隔離通信的典型應(yīng)用電路圖。試驗(yàn)結(jié)果表明，該設(shè)計(jì)可為電力現(xiàn)場、電力電子及儀器儀表的設(shè)計(jì)提供參考。
Abstract:
y comparing characteristics and applications area of various isolated digital communications， this article indicates advantages of plastic optical fiber in isolated digital communications. Using the standardized TOSLINK interface， it helps to control costs and difficulty in hardware development and design. Then it gives the hardware driver circuit of plastic optical fiber module， explains the noticed details in design process， gives results on the basis of the optical transceiver module voltage characteristics and frequency characteristics tests. Finally，it gives typical application circuit of the SPI communication port by using plastic optical fiber isolation .The results show that this design can be referenced for the power field， power electronics and instrumentation design.
提出了一種以ARM微處理器為控制核心的遠(yuǎn)程無線視頻監(jiān)控終端的設(shè)計(jì)方案，其監(jiān)控終端的硬件設(shè)計(jì)包括視頻采集處理、中央管理控制、無線傳輸3個模塊。并給出了監(jiān)控終端的軟件開發(fā)平臺和開發(fā)模式的系統(tǒng)啟動代碼、嵌入式Linux系統(tǒng)移植以及驅(qū)動程序和應(yīng)用程序。測試結(jié)果表明，該監(jiān)控終端設(shè)計(jì)方案合理、有效，基本滿足監(jiān)控需求。
Abstract:
A remote wireless video monitoring terminal design， which uses ARM microprocessor as its core control， is proposed in this paper.The hardware design of monitoring terminal system is composed of the video acquisition and processing module， the central management and control module， wireless transmission module.Meanwhile the monitoring terminal-s software development platform and development patterns are designed. Also the design of the system-s start codes， embedded Linux system-s transplantation process， driver and the corresponding applications are given. The results showed that the monitoring terminal design is reasonable， effective， basically meet monitoring requirements.
The LPC4350/30/20/10 are ARM Cortex-M4 based microcontrollers for embeddedapplications. The ARM Cortex-M4 is a next generation core that offers systemenhancements such as low power consumption, enhanced debug features, and a highlevel of support block integration.The LPC4350/30/20/10 operate at CPU frequencies of up to 150 MHz. The ARMCortex-M4 CPU incorporates a 3-stage pipeline, uses a Harvard architecture withseparate local instruction and data buses as well as a third bus for peripherals, andincludes an internal prefetch unit that supports speculative branching. The ARMCortex-M4 supports single-cycle digital signal processing and SIMD instructions. Ahardware floating-point processor is integrated in the core.The LPC4350/30/20/10 include an ARM Cortex-M0 coprocessor, up to 264 kB of datamemory, advanced configurable peripherals such as the State Configurable Timer (SCT)and the Serial General Purpose I/O (SGPIO) interface, two High-speed USB controllers,Ethernet, LCD, an external memory controller, and multiple digital and analog peripherals
This example provides a description of how to use the USART with hardware flowcontrol and communicate with the Hyperterminal.First, the USART2 sends the TxBuffer to the hyperterminal and still waiting fora string from the hyperterminal that you must enter which must end by '\r'character (keypad ENTER button). Each byte received is retransmitted to theHyperterminal. The string that you have entered is stored in the RxBuffer array. The receivebuffer have a RxBufferSize bytes as maximum.
The USART2 is configured as follow: - BaudRate = 115200 baud - Word Length = 8 Bits - One Stop Bit - No parity - hardware flow control enabled (RTS and CTS signals) - Receive and transmit enabled - USART Clock disabled - USART CPOL: Clock is active low - USART CPHA: Data is captured on the second edge - USART LastBit: The clock pulse of the last data bit is not output to the SCLK pin
通過以太網(wǎng)遠(yuǎn)程配置Nios II 處理器 應(yīng)用筆記
Firmware in embedded hardware systems is frequently updated over the Ethernet. For
embedded systems that comprise a discrete microprocessor and the devices it controls, the
firmware is the software image run by the microprocessor. When the embedded system
includes an FPGA, firmware updates include updates of the hardware image on the FPGA. If
the FPGA includes a Nios® II soft processor, you can upgrade both the Nios II processor—as
part of the FPGA image—and the software that the Nios II processor runs, in a single remote
configuration session.
Nios II 軟件開發(fā)人員手冊中的緩存和緊耦合存儲器部分
Nios® II embedded processor cores can contain instruction and data caches. This
chapter discusses cache-related issues that you need to consider to guarantee that
your program executes correctly on the Nios II processor. Fortunately, most software
based on the Nios II hardware abstraction layer (HAL) works correctly without any
special accommodations for caches. However, some software must manage the cache
directly. For code that needs direct control over the cache, the Nios II architecture
provides facilities to perform the following actions:
