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介紹高速電路的設(shè)計(jì)
標(biāo)簽：
high-Speed
Digital
Design
高速數(shù)字
上傳時(shí)間：
2013-12-02
上傳用戶：wentianyou
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protel 99se 使用技巧以及常見問題解決方法：里面有一些protel 99se 特別技巧，還有我們經(jīng)常遇到的一些問題！如何使一條走線至兩個(gè)不同位置零件的距離相同?
您可先在Design/Rule/High Speed/Matched Net Lengths的規(guī)則中來新增規(guī)則設(shè)定,最后再用Tools/EqualizeNet Lengths 來等長化即可。
Q02、在SCHLIB中造一零件其PIN的屬性，如何決定是Passive, Input, I/O, Hi-
Z,Power,…..？在HELP中能找到說明嗎？市面有關(guān) SIM？PLD？的書嗎？或貴公司有講義？
你可在零件庫自制零件時(shí)點(diǎn)選零件Pin腳,并在Electrical Type里,可以自行設(shè)定PIN的
屬性,您可參考臺(tái)科大的Protel sch 99se 里面有介紹關(guān)于SIM的內(nèi)容。
Q03、請問各位業(yè)界前輩,如何能順利讀取pcad8.6版的線路圖,煩請告知
Protel 99SE只能讀取P-CAD 2000的ASCII檔案格式,所以你必須先將P-CAD8.6版的格式轉(zhuǎn)為P-CAD 2000的檔案格式,才能讓Protel讀取。
Q04、請問我該如何標(biāo)示線徑大小的那個(gè)平方呢
你可以將格點(diǎn)大小設(shè)小,還有將字形大小縮小,再放置數(shù)字的平方位置即可。
Q05、請問我一次如何更改所有組件的字型
您可以點(diǎn)選其中一個(gè)組件字型,再用Global的方法就可以達(dá)成你的要求。
標(biāo)簽：
protel
99
se
使用技巧
上傳時(shí)間：
2015-01-01
上傳用戶：yxgi5
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Consumer display applications commonly use high-Speed LVDS interfaces to transfer videodata. Spread-spectrum clocking can be used to address electromagnetic compatibility (EMC)issues within these consumer devices. This application note uses Spartan®-6 FPGAs togenerate spread-spectrum clocks using the DCM_CLKGEN primitive.
標(biāo)簽：
Spartan
XAPP
1065
FPGA
上傳時(shí)間：
2013-11-01
上傳用戶：hjkhjk
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The Virtex-4 features, such as the programmable IDELAY and built-in FIFO support, simplifythe bridging of a high-Speed, PCI-X core to large amounts of DDR-SDRAM memory. Onechallenge is meeting the PCI-X target initial latency specification. PCI-X Protocol Addendum tothe PCI Local Bus Specification Revision 2.0a ([Ref 6]) dictates that when a target signals adata transfer, "the target must do so within 16 clocks of the assertion of FRAME#." PCItermination transactions, such as Split Response/Complete, are commonly used to meet thelatency specifications. This method adds complexity to the design, as well as additional systemlatency. Another solution is to increase the ratio of the memory frequency to the PCI-X busfrequency. However, this solution increases the required power and clock resource usage.
標(biāo)簽：
PCI-X
XAPP
DIMM
708
上傳時(shí)間：
2013-11-24
上傳用戶：18707733937
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波長信號的解調(diào)是實(shí)現(xiàn)光纖光柵傳感網(wǎng)絡(luò)的關(guān)鍵，基于現(xiàn)有的光纖光柵傳感器解調(diào)方法，提出一種基于FPGA的雙匹配光纖光柵解調(diào)方法，此系統(tǒng)是一種高速率、高精度、低成本的解調(diào)系統(tǒng)，并且通過引入雙匹配光柵有效地克服了雙值問題同時(shí)擴(kuò)大了檢測范圍。分析了光纖光柵的測溫原理并給出了該方案軟硬件設(shè)計(jì)，綜合考慮系統(tǒng)的解調(diào)精度和FPGA的處理速度給出了基于拉格朗日的曲線擬合算法。
Abstract:
Sensor is one of the most important application of the fiber grating. Wavelength signal demodulating is the key techniques to carry out fiber grating sensing network， based on several existing methods of fiber grating sensor demodulation inadequate， a two-match fiber grating demodulation method was presented. This system is a high-Speed， high precision， low-cost demodulation system. And by introducing a two-match grating effectively overcomes the problem of double value while expands the scope of testing. This paper analyzes the principle of fiber Bragg grating temperature and gives the software and hardware design of the program. Considering the system of demodulation accuracy and processing speed of FPGA，this paper gives the curve fitting algorithm based on Lagrange.
標(biāo)簽：
FPGA
光纖光柵
解調(diào)系統(tǒng)
上傳時(shí)間：
2013-10-10
上傳用戶：zxc23456789
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The LogiCORE™ GTP Wizard automates the task of creating HDL wrappers to configure the high-Speed serial GTP transceivers in Virtex™-5 LXT and SXT devices. The menu-driven interface allows one or more GTP transceivers to be configured using pre-definedtemplates for popular industry standards, or from scratch, to support a wide variety of custom protocols.The Wizard produces a wrapper, an example design, and a testbench for rapid integration and verification of the serial interface with your custom function
Features• Creates customized HDL wrappers to configureVirtex-5 RocketIO™ GTP transceivers• Users can configure Virtex-5 GTP transceivers toconform to industry standard protocols usingpredefined templates, or tailor the templates forcustom protocols• Included protocol templates provide support for thefollowing specifications: Aurora, CPRI, FibreChannel 1x, Gigabit Ethernet, HD-SDI, OBSAI,OC3, OC12, OC48, PCI Express® (PCIe®), SATA,SATA II, and XAUI• Automatically configures analog settings• Each custom wrapper includes example design, testbench; and both implementation and simulation scripts
標(biāo)簽：
Transceiver
Virtex
Wizar
GTP
上傳時(shí)間：
2013-10-20
上傳用戶：dave520l
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This document provides practical, common guidelines for incorporating PCI Express interconnect
layouts onto Printed Circuit Boards (PCB) ranging from 4-layer desktop baseboard designs to 10-
layer or more server baseboard designs. Guidelines and constraints in this document are intended
for use on both baseboard and add-in card PCB designs. This includes interconnects between PCI
Express devices located on the same baseboard (chip-to-chip routing) and interconnects between
a PCI Express device located “down” on the baseboard and a device located “up” on an add-in
card attached through a connector.
This document is intended to cover all major components of the physical interconnect including
design guidelines for the PCB traces, vias and AC coupling capacitors, as well as add-in card
edge-finger and connector considerations. The intent of the guidelines and examples is to help
ensure that good high-Speed signal design practices are used and that the timing/jitter and
loss/attenuation budgets can also be met from end-to-end across the PCI Express interconnect.
However, while general physical guidelines and suggestions are given, they may not necessarily
guarantee adequate performance of the interconnect for all layouts and implementations.
Therefore, designers should consider modeling and simulation of the interconnect in order to
ensure compliance to all applicable specifications.
The document is composed of two main sections. The first section provides an overview of
general topology and interconnect guidelines. The second section concentrates on physical layout
constraints where bulleted items at the beginning of a topic highlight important constraints, while
the narrative that follows offers additional insight.
標(biāo)簽：
pci
PCB
設(shè)計(jì)規(guī)范
上傳時(shí)間：
2014-01-24
上傳用戶：s363994250
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Q01、如何使一條走線至兩個(gè)不同位置零件的距離相同?
您可先在Design/Rule/High Speed/Matched Net Lengths的規(guī)則中來新增規(guī)則設(shè)定,最
后再用Tools/EqualizeNet Lengths 來等長化即可。
Q02、在SCHLIB中造一零件其PIN的屬性，如何決定是Passive, Input, I/O, Hi-
Z,Power,…..？在HELP中能找到說明嗎？市面有關(guān) SIM？PLD？的書嗎？或貴公司有講義？
你可在零件庫自制零件時(shí)點(diǎn)選零件Pin腳,并在Electrical Type里,可以自行設(shè)定PIN的
屬性,您可參考臺(tái)科大的Protel sch 99se 里 面有介紹關(guān)于SIM的內(nèi)容。
Q03、請問各位業(yè)界前輩,如何能順利讀取pcad8.6版的線路圖,煩請告知
Protel 99SE只能讀取P-CAD 2000的ASCII檔案格式,所以你必須先將P-CAD8.6版的格式
轉(zhuǎn)為P-CAD 2000的檔案格式,才能讓Protel讀取。
標(biāo)簽：
Protel
上傳時(shí)間：
2013-11-07
上傳用戶：tangsiyun
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The data plane of the reference design consists of a configurable multi-channel XBERT modulethat generates and checks high-Speed serial data transmitted and received by the MGTs. Eachchannel in the XBERT module consists of two MGTs (MGTA and MGTB), which physicallyoccupy one MGT tile in the Virtex-4 FPGA. Each MGT has its own pattern checker, but bothMGTs in a channel share the same pattern generator. Each channel can load a differentpattern. The MGT serial rate depends on the reference clock frequency and the internal PMAdivider settings. The reference design can be scaled anywhere from one channel (two MGTs)to twelve channels (twenty-four MGTs).
標(biāo)簽：
RocketIO
Virtex
XAPP
713
上傳時(shí)間：
2013-12-25
上傳用戶：jkhjkh1982
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The HD66773, controller driver LSI, displays 132RGB-by-176 dot graphics on TFT displays in 260,000
colors. The HD66773’s bit-operation functions, 18-bit high-Speed bus interface, and high-Speed RAMwrite
functions enable efficient data transfer and high-Speed rewriting of data to the graphic RAM.
標(biāo)簽：
displays
controller
graphics
RGB-by
上傳時(shí)間：
2014-06-19
上傳用戶：stvnash
