This application note describes the implementation of a two-dimensional Rank Order filter. Thereference design includes the RTL VHDL implementation of an efficient sorting algorithm. Thedesign is parameterizable for input/output precision, color standards, filter kernel size,maximum horizontal resolution, and implementation options. The rank to be selected can bemodified dynamically, and the actual horizontal resolution is picked up automatically from theinput synchronization signals. The design has a fully synchronous interface through the ce, clk,and rst ports.
上傳時間： 2013-12-14
上傳用戶：逗逗666
Consumer display applications commonly use high-speed LVDS interfaces to transfer videodata. Spread-spectrum clocking can be used to address electromagnetic compatibility (EMC)issues within these consumer devices. This application note uses Spartan®-6 FPGAs togenerate spread-spectrum clocks using the DCM_CLKGEN primitive.
標(biāo)簽： Spartan XAPP 1065 FPGA
上傳時間： 2013-11-01
上傳用戶：hjkhjk
The Virtex-4 features, such as the programmable IDELAY and built-in FIFO support, simplifythe bridging of a high-speed, PCI-X core to large amounts of DDR-SDRAM memory. Onechallenge is meeting the PCI-X target initial latency specification. PCI-X Protocol Addendum tothe PCI Local Bus Specification Revision 2.0a ([Ref 6]) dictates that when a target signals adata transfer, "the target must do so within 16 clocks of the assertion of FRAME#." PCItermination transactions, such as Split Response/Complete, are commonly used to meet thelatency specifications. This method adds complexity to the design, as well as additional systemlatency. Another solution is to increase the ratio of the memory frequency to the PCI-X busfrequency. However, this solution increases the required power and clock resource usage.
上傳時間： 2013-11-24
上傳用戶：18707733937
The SDI standards are the predominant standards for uncompressed digital videointerfaces in the broadcast studio and video production center. The first SDI standard,SD-SDI, allowed standard-definition digital video to be transported over the coaxial cableinfrastructure initially installed in studios to carry analog video. Next, HD-SDI wasto support high-definition video. Finally, dual link HD-SDI and 3G-SDIdoubled the bandwidth of HD-SDI to support 1080p (50 Hz and 60 Hz) and other videoformats requiring more bandwidth than HD-SDI provides.
上傳時間： 2013-12-08
上傳用戶：liansi
This application note covers the design considerations of a system using the performance features of the LogiCORE™ IP Advanced eXtensible Interface (AXI) Interconnect core. The design focuses on high system throughput through the AXI Interconnect core with F MAX and area optimizations in certain portions of the design. The design uses five AXI video direct memory access (VDMA) engines to simultaneously move 10 streams (five transmit video streams and five receive video streams), each in 1920 x 1080p format, 60 Hz refresh rate, and up to 32 data bits per pixel. Each VDMA is driven from a video test pattern generator (TPG) with a video timing controller (VTC) block to set up the necessary video timing signals. Data read by each AXI VDMA is sent to a common on-screen display (OSD) core capable of multiplexing or overlaying multiple video streams to a single output video stream. The output of the OSD core drives the DVI video display interface on the board. Performance monitor blocks are added to capture performance data. All 10 video streams moved by the AXI VDMA blocks are buffered through a shared DDR3 SDRAM memory and are controlled by a MicroBlaze™ processor. The reference system is targeted for the Virtex-6 XC6VLX240TFF1156-1 FPGA on the Xilinx® ML605 Rev D evaluation board
標(biāo)簽： XAPP 740 AXI 互聯(lián)
上傳時間： 2013-11-23
上傳用戶：shen_dafa
XAPP520將符合2.5V和3.3V I/O標(biāo)準(zhǔn)的7系列FPGA高性能I/O Bank進行連接 The I/Os in Xilinx® 7 series FPGAs are classified as either high range (HR) or high performance (HP) banks. HR I/O banks can be operated from 1.2V to 3.3V, whereas HP I/O banks are optimized for operation between 1.2V and 1.8V. In circumstances that require an HP 1.8V I/O bank to interface with 2.5V or 3.3V logic, a range of options can be deployed. This application note describes methodologies for interfacing 7 series HP I/O banks with 2.5V and 3.3V systems
上傳時間： 2013-11-06
上傳用戶：wentianyou
WP409利用Xilinx FPGA打造出高端比特精度和周期精度浮點DSP算法實現(xiàn)方案： High-Level Implementation of Bit- and Cycle-Accurate Floating-Point DSP Algorithms with Xilinx FPGAs
上傳時間： 2013-10-21
上傳用戶：huql11633
Xilinx Next Generation 28 nm FPGA Technology Overview Xilinx has chosen 28 nm high-κ metal gate (HKMG) highperformance,low-power process technology and combined it with a new unified ASMBL™ architecture to create a new generation of FPGAs that offer lower power and higher performance. These devices enable unprecedented levels of integration and bandwidth and provide system architects and designers a fully programmable alternative to ASSPs and ASICs.
上傳時間： 2013-12-07
上傳用戶：bruce
FPGAs have changed dramatically since Xilinx first introduced them just 15 years ago. In thepast, FPGA were primarily used for prototyping and lower volume applications; custom ASICswere used for high volume, cost sensitive designs. FPGAs had also been too expensive and tooslow for many applications, let alone for System Level Integration (SLI). Plus, the development
標(biāo)簽： Methodology Design Reuse FPGA
上傳時間： 2013-11-01
上傳用戶：shawvi
波長信號的解調(diào)是實現(xiàn)光纖光柵傳感網(wǎng)絡(luò)的關(guān)鍵，基于現(xiàn)有的光纖光柵傳感器解調(diào)方法，提出一種基于FPGA的雙匹配光纖光柵解調(diào)方法，此系統(tǒng)是一種高速率、高精度、低成本的解調(diào)系統(tǒng)，并且通過引入雙匹配光柵有效地克服了雙值問題同時擴大了檢測范圍。分析了光纖光柵的測溫原理并給出了該方案軟硬件設(shè)計，綜合考慮系統(tǒng)的解調(diào)精度和FPGA的處理速度給出了基于拉格朗日的曲線擬合算法。 Abstract: Sensor is one of the most important application of the fiber grating. Wavelength signal demodulating is the key techniques to carry out fiber grating sensing network， based on several existing methods of fiber grating sensor demodulation inadequate， a two-match fiber grating demodulation method was presented. This system is a high-speed， high precision， low-cost demodulation system. And by introducing a two-match grating effectively overcomes the problem of double value while expands the scope of testing. This paper analyzes the principle of fiber Bragg grating temperature and gives the software and hardware design of the program. Considering the system of demodulation accuracy and processing speed of FPGA，this paper gives the curve fitting algorithm based on Lagrange.
標(biāo)簽： FPGA 光纖光柵 解調(diào)系統(tǒng)
上傳時間： 2013-10-10
上傳用戶：zxc23456789
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