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insertion

  • N-path+Filtering

    his research aims at creating broadband tunable, fully integrated filters for the application of cognitive radio and signal classification receivers. The approach under study is the N-path filter technique which is capable of translating a baseband impedance to a reference frequency creating a tunable filter. The traditional N-path filter suffers from fundamental architectural limitations, namely : a trade-off between insertion loss and out-of-band rejection, reference clock feed- through, and jammer power handling limitations. In the first approach, the fundamental trade- off of the traditional N-path filter between insertion loss and out-of-band rejection is improved by a transmission line (T-line) N-path filter technique. 

    標(biāo)簽: Filtering N-path

    上傳時(shí)間: 2020-05-31

    上傳用戶(hù):shancjb

  • I2C熱插拔和SMBus緩沖器

    The NCA9511 is a hot-swappable I2C bus buffer that  supports I/O card insertion into a live backplane without  corruption of the data and clock buses.

    標(biāo)簽: SMBus I2C 熱插拔 緩沖器

    上傳時(shí)間: 2021-01-26

    上傳用戶(hù):

  • CPU可測(cè)試性設(shè)計(jì)

    可測(cè)試性設(shè)計(jì)(Design-For-Testability,DFT)已經(jīng)成為芯片設(shè)計(jì)中不可或缺的重要組成部分。它通過(guò)在芯片的邏輯設(shè)計(jì)中加入測(cè)試邏輯提高芯片的可測(cè)試性。在高性能通用 CPU 的設(shè)計(jì)中,可測(cè)試性設(shè)計(jì)技術(shù)得到了廣泛的應(yīng)用。本文結(jié)合幾款流行的 CPU,綜述了可應(yīng)用于通用 CPU 等高性能芯片設(shè)計(jì)中的各種可測(cè)試性方法,包括掃描設(shè)計(jì)(Scan Design),內(nèi)建自測(cè)試(Built-In Self-Test,BIST),測(cè)試點(diǎn)插入(Test Point insertion),與 IEEE 1149.1標(biāo)準(zhǔn)兼容的邊界掃描設(shè)計(jì)(Boundary Scan Design,BSD)等技術(shù)。

    標(biāo)簽: 可測(cè)試性設(shè)計(jì) CPU

    上傳時(shí)間: 2021-10-15

    上傳用戶(hù):

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