This application note covers the design considerations of a system using the performance features of the LogiCORE™ IP Advanced eXtensible interface (AXI) Interconnect core. The design focuses on high system throughput through the AXI Interconnect core with F MAX and area optimizations in certain portions of the design. The design uses five AXI video direct memory access (VDMA) engines to simultaneously move 10 streams (five transmit video streams and five receive video streams), each in 1920 x 1080p format, 60 Hz refresh rate, and up to 32 data bits per pixel. Each VDMA is driven from a video test pattern generator (TPG) with a video timing controller (VTC) block to set up the necessary video timing signals. Data read by each AXI VDMA is sent to a common on-screen display (OSD) core capable of multiplexing or overlaying multiple video streams to a single output video stream. The output of the OSD core drives the DVI video display interface on the board. Performance monitor blocks are added to capture performance data. All 10 video streams moved by the AXI VDMA blocks are buffered through a shared DDR3 SDRAM memory and are controlled by a MicroBlaze™ processor. The reference system is targeted for the Virtex-6 XC6VLX240TFF1156-1 FPGA on the Xilinx® ML605 Rev D evaluation board
標(biāo)簽： XAPP 740 AXI 互聯(lián)
上傳時(shí)間： 2013-11-23
上傳用戶：shen_dafa
XAPP520將符合2.5V和3.3V I/O標(biāo)準(zhǔn)的7系列FPGA高性能I/O Bank進(jìn)行連接 The I/Os in Xilinx® 7 series FPGAs are classified as either high range (HR) or high performance (HP) banks. HR I/O banks can be operated from 1.2V to 3.3V, whereas HP I/O banks are optimized for operation between 1.2V and 1.8V. In circumstances that require an HP 1.8V I/O bank to interface with 2.5V or 3.3V logic, a range of options can be deployed. This application note describes methodologies for interfacing 7 series HP I/O banks with 2.5V and 3.3V systems
上傳時(shí)間： 2013-11-06
上傳用戶：wentianyou
Xilinx FPGAs require at least two power supplies: VCCINTfor core circuitry and VCCO for I/O interface. For the latestXilinx FPGAs, including Virtex-II Pro, Virtex-II and Spartan-3, a third auxiliary supply, VCCAUX may be needed. Inmost cases, VCCAUX can share a power supply with VCCO.The core voltages, VCCINT, for most Xilinx FPGAs, rangefrom 1.2V to 2.5V. Some mature products have 3V, 3.3Vor 5V core voltages. Table 1 shows the core voltagerequirement for most of the FPGA device families. TypicalI/O voltages (VCCO) vary from 1.2V to 3.3V. The auxiliaryvoltage VCCAUX is 2.5V for Virtex-II Pro and Spartan-3, andis 3.3V for Virtex-II.
上傳時(shí)間： 2013-10-22
上傳用戶：aeiouetla
【摘要】本文結(jié)合作者多年的印制板設(shè)計(jì)經(jīng)驗(yàn)，著重印制板的電氣性能，從印制板穩(wěn)定性、可靠性方面，來(lái)討論多層印制板設(shè)計(jì)的基本要求。【關(guān)鍵詞】印制電路板；表面貼裝器件；高密度互連；通孔【Key words】Printed Circuit Board；Surface Mounting Device；High Density interface；Via一．概述印制板（PCB－Printed Circuit Board）也叫印制電路板、印刷電路板。多層印制板，就是指兩層以上的印制板，它是由幾層絕緣基板上的連接導(dǎo)線和裝配焊接電子元件用的焊盤組成，既具有導(dǎo)通各層線路，又具有相互間絕緣的作用。隨著SMT（表面安裝技術(shù)）的不斷發(fā)展，以及新一代SMD（表面安裝器件）的不斷推出，如QFP、QFN、CSP、BGA（特別是MBGA），使電子產(chǎn)品更加智能化、小型化，因而推動(dòng)了PCB工業(yè)技術(shù)的重大改革和進(jìn)步。自1991年IBM公司首先成功開(kāi)發(fā)出高密度多層板（SLC）以來(lái)，各國(guó)各大集團(tuán)也相繼開(kāi)發(fā)出各種各樣的高密度互連（HDI）微孔板。這些加工技術(shù)的迅猛發(fā)展，促使了PCB的設(shè)計(jì)已逐漸向多層、高密度布線的方向發(fā)展。多層印制板以其設(shè)計(jì)靈活、穩(wěn)定可靠的電氣性能和優(yōu)越的經(jīng)濟(jì)性能，現(xiàn)已廣泛應(yīng)用于電子產(chǎn)品的生產(chǎn)制造中。下面，作者以多年設(shè)計(jì)印制板的經(jīng)驗(yàn)，著重印制板的電氣性能，結(jié)合工藝要求，從印制板穩(wěn)定性、可靠性方面，來(lái)談?wù)劧鄬又瓢逶O(shè)計(jì)的基本要領(lǐng)。
上傳時(shí)間： 2013-10-08
上傳用戶：zhishenglu
The LogiCORE™ GTP Wizard automates the task of creating HDL wrappers to configure the high-speed serial GTP transceivers in Virtex™-5 LXT and SXT devices. The menu-driven interface allows one or more GTP transceivers to be configured using pre-definedtemplates for popular industry standards, or from scratch, to support a wide variety of custom protocols.The Wizard produces a wrapper, an example design, and a testbench for rapid integration and verification of the serial interface with your custom function Features• Creates customized HDL wrappers to configureVirtex-5 RocketIO™ GTP transceivers• Users can configure Virtex-5 GTP transceivers toconform to industry standard protocols usingpredefined templates, or tailor the templates forcustom protocols• Included protocol templates provide support for thefollowing specifications: Aurora, CPRI, FibreChannel 1x, Gigabit Ethernet, HD-SDI, OBSAI,OC3, OC12, OC48, PCI Express® (PCIe®), SATA,SATA II, and XAUI• Automatically configures analog settings• Each custom wrapper includes example design, testbench; and both implementation and simulation scripts
標(biāo)簽： Transceiver Virtex Wizar GTP
上傳時(shí)間： 2013-10-20
上傳用戶：dave520l
a8259 可編程中斷控制 altera提供 The a8259 is designed to simplify the implementation of the interrupt interface in 8088 and 8086 based microcomputer systems. The device is known as a programmable interrupt controller. The a8259 receives and prioritizes up to 8 interrupts, and in the cascade mode, this can be expanded up to 64 interrupts. An asynchronous reset and a clock input have been added to improve operation and reliability.
上傳時(shí)間： 2015-01-02
上傳用戶：panpanpan
The high defi nition multimedia interface (HDMI) is fastbecoming the de facto standard for passing digitalaudio and video data in home entertainment systems.This standard includes an I2C type bus called a displaydata channel (DDC) that is used to pass extended digitalinterface data (EDID) from the sinkdevice (such as adigital TV) to the source device (such as a digital A/Vreceiver). EDID includes vital information on the digitaldata formats that the sink device can accept. The HDMIspecifi cation requires that devices have less than 50pFof input capacitance on their DDC bus lines, which canbe very diffi cult to meet. The LTC®4300A’s capacitancebuffering feature allows devices to pass the HDMI DDCinput capacitance compliance test with ease.
上傳時(shí)間： 2013-11-21
上傳用戶：tian126vip
SPI（Serial Peripheral interface，串行外圍接口）是Motorola公司提出的外圍接口協(xié)議，它采用一個(gè)串行、同步、全雙工的通信方式，解決了微處理器和外設(shè)之間的串行通信問(wèn)題，并且可以和多個(gè)外設(shè)直接通信，具有配置靈活，結(jié)構(gòu)簡(jiǎn)單等優(yōu)點(diǎn)。根據(jù)全功能SPI總線的特點(diǎn)，設(shè)計(jì)的SPI接口可以最大發(fā)送和接收16位數(shù)據(jù)；在主模式和從模式下SPI模塊的時(shí)鐘頻率最大可以達(dá)到系統(tǒng)時(shí)鐘的1/4，并且在主模式下可以提供具有四種不同相位和極性的時(shí)鐘供從模塊選擇；可以同時(shí)進(jìn)行發(fā)送和接收操作，擁有中斷標(biāo)志位和溢出中斷標(biāo)志位。
標(biāo)簽： SPI 接口的設(shè)計(jì)
上傳時(shí)間： 2013-11-11
上傳用戶：himbly
Abstract: How can an interface change a happy face to a sad face? Engineers have happy faces when an interface works properly.Sad faces indicate failure somewhere. Because interfaces between microprocessors and ICs are simple—even easy—they are oftenignored until interface failure causes sad faces all around. In this article, we discuss a common SPI error that can be almostimpossible to find in a large system. Links to interface tutorial information are provided for complete information. Noise as a systemissue and ICs to minimize its effects are also described.
上傳時(shí)間： 2013-11-18
上傳用戶：zgz317
A collection of interface applications between various microprocessors/ controllers and the LTC1090 family of data acquisition systems. The note is divided into sections specific to each interface.
上傳時(shí)間： 2013-11-08
上傳用戶：sssnaxie
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