亚洲欧美第一页_禁久久精品乱码_粉嫩av一区二区三区免费野_久草精品视频

蟲蟲首頁| 資源下載| 資源專輯| 精品軟件
登錄| 注冊

您現在的位置是:蟲蟲下載站 > 資源下載 > 其他書籍 > 關于FPGA流水線設計的論文 This work investigates the use of very deep pipelines for implementing circuits in

關于FPGA流水線設計的論文 This work investigates the use of very deep pipelines for implementing circuits in

資 源 簡 介

關于FPGA流水線設計的論文 This work investigates the use of very deep pipelines for implementing circuits in FPGAs, where each pipeline stage is limited to a single FPGA logic element (LE). The architecture and VHDL design of a parameterized integer array multiplier is presented and also an IEEE 754 compliant 32-bit floating-point multiplier. We show how to write VHDL cells that implement such approach, and how the array multiplier architecture was adapted. Synthesis and simulation were performed for Altera Apex20KE devices, although the VHDL code should be portable to other devices. For this family, a 16 bit integer multiplier achieves a frequency of 266MHz, while the floating point unit reaches 235MHz, performing 235 MFLOPS in an FPGA. Additional cells are inserted to synchronize data, what imposes significant area penalties. This and other considerations to apply the technique in real designs are also addressed.

相 關 資 源

主站蜘蛛池模板: 拉萨市| 剑河县| 乐清市| 乡宁县| 文成县| 赫章县| 东辽县| 扶绥县| 德令哈市| 海淀区| 揭西县| 台州市| 滦平县| 河津市| 东丽区| 梁平县| 当阳市| 潜江市| 区。| 舞阳县| 石首市| 巧家县| 聂荣县| 元阳县| 蒲江县| 衡阳县| 汝南县| 泸水县| 永定县| 七台河市| 航空| 包头市| 武夷山市| 阳城县| 浪卡子县| 霸州市| 东丽区| 庆城县| 界首市| 聊城市| 漯河市|