此程序是例程為基于二進制算術(shù)編碼的解碼程序，適用于概率模型為JBIG的編碼模型。
標(biāo)簽： 程序 二進制 算術(shù)編碼 解碼程序
上傳時間： 2017-02-09
上傳用戶：sardinescn
Custom Visual Basic Packager and Installer for Visual Basic Developers. This is a group of standard exe projects 1. Packager 2. Setup1 The packager works like Visual basic Application deployment Wizard. And the setup1 project is used for the installation of the package. This project demonstrates how to compile visual basic project without launching the Vb6 kit and retrieving the dependency Files of any Visual basic project (although roughly done without any specific algorithm), Somebody can help me with this. I don’ t have time for the project, so I don’ t want any comment on the code indentation or arrangement and variable scoping. Comments are in the code therefore it would not be a problem to understand the code. If anyone wants to vote, I will like it Oh! I found some of the setup1 code and modify it with new features, so i have no or less credit for the setup1 project I felt like sharing code with PSCites. Thats why I made it
標(biāo)簽： Visual Basic Developers Installer
上傳時間： 2017-02-26
上傳用戶：FreeSky
用戶界面設(shè)計英文書籍，名字叫“custom interface kit"
標(biāo)簽： 用戶界面設(shè)計 書籍 英文
上傳時間： 2014-01-17
上傳用戶：363186
It is a first time code being developed to designers who want to get your DDR2 SDRAM on-board in Spartan 3AN Starter Kit - Diligent fully working.
標(biāo)簽： developed designers on-board first
上傳時間： 2014-11-18
上傳用戶：guanliya
Java Card API，Development Kit for the Java CardTM Platform，在開發(fā)java卡片的時候，需要把JChome指向在這里
上傳時間： 2014-11-18
上傳用戶：zhaoq123
it is a verilog code written for MAX1886 ADC interin modelsim simulator and it will synthesize in xinlix ise 8.2i.i have tested it om my kit.
標(biāo)簽： synthesize simulator modelsim interin
上傳時間： 2017-03-22
上傳用戶：洛木卓
it is a verilog code written for digital watch in modelsim simulator and it will synthesize in xinlix ise 8.2i.i have tested it om my kit.[i mae my own kit for spartan2 device]
標(biāo)簽： synthesize simulator modelsim digital
上傳時間： 2014-01-10
上傳用戶：kernaling
it is a verilog code written for FIFO in modelsim simulator and it will synthesize in xinlix ise 8.2i.i have tested it om my kit.[i mae my own kit for spartan2 device].you can use this code in any DSP project in which data entry is required.
標(biāo)簽： synthesize simulator modelsim verilog
上傳時間： 2014-06-26
上傳用戶：zhuyibin
it is a verilog code written for traffic light controller will synthesize in xinlix ise 8.2i.i have tested it om my kit.[i mae my own kit for spartan2 device].it is a state machine based code.
標(biāo)簽： controller synthesize verilog traffic
上傳時間： 2017-03-22
上傳用戶：xymbian
it is a verilog code written for MELAY state machine based UART and it wll synthesize in xinlix ise 8.2i.i have tested it om my kit.[i mae my own kit for spartan2 device]
標(biāo)簽： synthesize verilog machine written
上傳時間： 2013-12-11
上傳用戶：yepeng139
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