以AVR單片機ATmega8和USB接口器件PDIUSBD12為核心，基于標準的USB1.1協議，設計一種通用USB接口模塊，以滿足嵌入式系統中對USB接口的需求。對模塊的硬件電路或單片機固件程序的硬件接口層稍加修改即可用于其他各種微處理器。該模塊可為各種嵌入式系統增加USB接口,實現與USB主機系統通信。
Abstract:
Based on AVR microcontroller ATmega8 and USB interface chip PDIUSBD12, a general USB interface module is designed according to USB1.1 protocol for various requirements of embedded systems. Only with few modifications in circuit or hardware abstract layer of firmware, the module can be used on many types of microprocessors. All kinds of embedded systems can realize high speed and stable communication with USB host systems, owing to the facility of this module.
The NCV7356 is a physical layer device for a single wire data linkcapable of operating with various Carrier Sense Multiple Accesswith Collision Resolution (CSMA/CR) protocols such as the BoschController Area Network (CAN) version 2.0. This serial data linknetwork is intended for use in applications where high data rate is notrequired and a lower data rate can achieve cost reductions in both thephysical media components and in the microprocessor and/ordedicated logic devices which use the network.The network shall be able to operate in either the normal data ratemode or a high-speed data download mode for assembly line andservice data transfer operations. The high-speed mode is onlyintended to be operational when the bus is attached to an off-boardservice node. This node shall provide temporary bus electrical loadswhich facilitate higher speed operation. Such temporary loads shouldbe removed when not performing download operations.The bit rate for normal communications is typically 33 kbit/s, forhigh-speed transmissions like described above a typical bit rate of83 kbit/s is recommended. The NCV7356 features undervoltagelockout, timeout for faulty blocked input signals, output blankingtime in case of bus ringing and a very low sleep mode current.
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ExpressPCB 是一款免費的PCB設計軟件，簡單實使。可以畫雙層板。
Our Free PCB software is a snap to learn and use. For the first time, designing circuit boards is simple for the beginner and efficient for the professional.
Our board manufacturing service makes top quality two and four layer PCBs. Use our MiniBoard service and pay only $51 for three boards (plus $8 shipping).
Nios II 軟件開發人員手冊中的緩存和緊耦合存儲器部分
Nios® II embedded processor cores can contain instruction and data caches. This
chapter discusses cache-related issues that you need to consider to guarantee that
your program executes correctly on the Nios II processor. Fortunately, most software
based on the Nios II hardware abstraction layer (HAL) works correctly without any
special accommodations for caches. However, some software must manage the cache
directly. For code that needs direct control over the cache, the Nios II architecture
provides facilities to perform the following actions:
