RISC-V 指令集手冊 卷 1：用戶級指令集體系結(jié)構(gòu)（User-Level ISA）
標(biāo)簽： RISC-V 指令集
上傳時間： 2022-06-18
上傳用戶：XuVshu
JPEG2000是由ISO/ITU-T組織下的IEC JTC1/SC29/WG1小組制定的下一代靜止圖像壓縮標(biāo)準(zhǔn).與JPEG(Joint Photographic Experts Group)相比,JPEG2000能夠提供更好的數(shù)據(jù)壓縮比,并且提供了一些JPEG所不具有的功能[1].JPEG2000具有的多種特性使得它具有廣泛的應(yīng)用前景.但是,JPEG2000是一個復(fù)雜編碼系統(tǒng),目前為止的軟件實現(xiàn)方案的執(zhí)行時間和所需的存儲量較大,若想將JPEG2000應(yīng)用于實際中,有著較大的困難,而用硬件電路實現(xiàn)JPEG2000或者其中的某些模塊,必然能夠減少JPEG200的執(zhí)行時間,因而具有重要的意義.本文首先簡單介紹了JPEG2000這一新的靜止圖像壓縮標(biāo)準(zhǔn),然后對算術(shù)編碼的原理及實現(xiàn)算法進行了深入的研究,并重點探討了JPEG2000中算術(shù)編碼的硬件實現(xiàn)問題,給出了一種硬件最優(yōu)化的算術(shù)編碼實現(xiàn)方案.最后使用硬件描述語言(Very High Speed Integrated Circuit Hardware Description Language,VHDL)在寄存器傳輸級(Register Transfer Level,RTL描述了該硬件最優(yōu)化的算術(shù)編碼實現(xiàn)方案,并以Altera 20K200E FPGA為基礎(chǔ),在Active-HDL環(huán)境中進行了功能仿真,在Quartus Ⅱ集成開發(fā)環(huán)境下完成了綜合以及后仿真,綜合得到的最高工作時鐘頻率達45.81MHz.在相同的輸入條件下,輸出結(jié)果表明,本文設(shè)計的硬件算術(shù)編碼器與實現(xiàn)JPEG2000的軟件:Jasper[2]中的算術(shù)編碼模塊相比,處理時間縮短了30﹪左右.因而本文的研究對于JPEG2000應(yīng)用于數(shù)字監(jiān)控系統(tǒng)等實際應(yīng)用有著重要的意義.
標(biāo)簽： JPEG 2000 FPGA 算術(shù)編碼
上傳時間： 2013-05-16
上傳用戶：671145514
In this paper, we discuss efficient coding and design styles using verilog. This can beimmensely helpful for any digital designer initiating designs. Here, we address different problems rangingfrom RTL-Gate Level simulation mismatch to race conditions in writing behavioral models. All theseproblems are accompanied by an example to have a better idea, and these can be taken care off if thesecoding guidelines are followed. Discussion of all the techniques is beyond the scope of this paper, however,here we try to cover a few of them.
標(biāo)簽： Efficient Verilog Digital Coding
上傳時間： 2013-11-22
上傳用戶：han_zh
This document was developed under the Standard Hardware and Reliability Program (SHARP) TechnologyIndependent Representation of Electronic Products (TIREP) project. It is intended for use by VHSIC HardwareDescription Language (VHDL) design engineers and is offered as guidance for the development of VHDL modelswhich are compliant with the VHDL Data Item Description (DID DI-EGDS-80811) and which can be providedto manufacturing engineering personnel for the development of production data and the subsequent productionof hardware. Most VHDL modeling performed to date has been concentrated at either the component level orat the conceptual system level. The assembly and sub-assembly levels have been largely disregarded. Under theSHARP TIREP project, an attempt has been made to help close this gap. The TIREP models are based upon lowcomplexity Standard Electronic Modules (SEM) of the format A configuration. Although these modules are quitesimple, it is felt that the lessons learned offer guidance which can readily be applied to a wide range of assemblytypes and complexities.
標(biāo)簽： Modelling Guide Navy VHDL
上傳時間： 2014-12-23
上傳用戶：xinhaoshan2016
Methods for designing a maintenance simulation training system for certain kind of radio are introduced. Fault modeling method is used to establish the fault database. The system sets up some typical failures， follow the prompts trainers can locate the fault source and confirm the type to accomplish corresponding fault maintenance training. A training evaluation means is given to examining and evaluating the training performance. The system intuitively and vividly shows the fault maintenance process， it can not only be used in teaching， but also in daily maintenance training to efficiently improve the maintenance operation level. Graphical programming language LabVIEW is used to develop the system platform.
標(biāo)簽： 電臺維修 模擬訓(xùn)練 方法研究 系統(tǒng)設(shè)計
上傳時間： 2013-11-19
上傳用戶：3294322651
為了滿足現(xiàn)代高速通信中頻率快速轉(zhuǎn)換的需求，基于坐標(biāo)旋轉(zhuǎn)數(shù)字計算（CORDIC，Coordinate Rotation Digital Computer）算法完成正交直接數(shù)字頻率合成（ODDFS，Orthogonal Direct Digital Frequency Synthesizer）電路設(shè)計方案。采用MATLAB和Xilinx System Generator開發(fā)工具搭建電路的系統(tǒng)模型，通過現(xiàn)場可編程門陣列（FPGA，F(xiàn)ield Programmable Gate Array）完成電路的寄存器傳輸級（RTL，Register Transfer Level）驗證，仿真結(jié)果表明電路設(shè)計具有很高的有效性和可行性。
標(biāo)簽： CORDIC ODDFS 算法 電路設(shè)計
上傳時間： 2013-11-09
上傳用戶：hfnishi
This paper presents a space vector modulation(SVM)-based switching strategy for a three-level neutral point clamped (NPC) converter that is adapted as a STATCOM.
標(biāo)簽： STATCOM 三電平 變換器 空間矢量
上傳時間： 2013-10-20
上傳用戶：zyt
The LTC®1966 is a true RMS-to-DC converter that uses aDS computational technique to make it dramatically simplerto use, significantly more accurate, lower in powerconsumption and more flexible than conventional logantilogRMS-to-DC converters. The LTC1966 RMS-to-DCconverter has an input signal range from 5mVRMS to1.5VRMS (a 50dB dynamic range with a single 5V supplyrail) and a 3dB bandwidth of 800kHz with signal crestfactors up to four.
標(biāo)簽： 真有效值 轉(zhuǎn)換器 自動調(diào)節(jié)
上傳時間： 2013-10-12
上傳用戶：qilin
This publication represents the largest LTC commitmentto an application note to date. No other application noteabsorbed as much effort, took so long or cost so much.This level of activity is justified by our belief that high speedmonolithic amplifiers greatly interest users.
標(biāo)簽： 高速放大器
上傳時間： 2014-01-07
上傳用戶：wfl_yy
ANALOG INPUT BANDWIDTH is a measure of the frequencyat which the reconstructed output fundamental drops3 dB below its low frequency value for a full scale input. Thetest is performed with fIN equal to 100 kHz plus integer multiplesof fCLK. The input frequency at which the output is −3dB relative to the low frequency input signal is the full powerbandwidth.APERTURE JITTER is the variation in aperture delay fromsample to sample. Aperture jitter shows up as input noise.APERTURE DELAY See Sampling Delay.BOTTOM OFFSET is the difference between the input voltagethat just causes the output code to transition to the firstcode and the negative reference voltage. Bottom Offset isdefined as EOB = VZT–VRB, where VZT is the first code transitioninput voltage and VRB is the lower reference voltage.Note that this is different from the normal Zero Scale Error.CONVERSION LATENCY See PIPELINE DELAY.CONVERSION TIME is the time required for a completemeasurement by an analog-to-digital converter. Since theConversion Time does not include acquisition time, multiplexerset up time, or other elements of a complete conversioncycle, the conversion time may be less than theThroughput Time.DC COMMON-MODE ERROR is a specification which appliesto ADCs with differential inputs. It is the change in theoutput code that occurs when the analog voltages on the twoinputs are changed by an equal amount. It is usually expressed in LSBs.
標(biāo)簽： Converter Defi ADC 轉(zhuǎn)換器
上傳時間： 2013-11-12
上傳用戶：pans0ul
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