The NXP LPC315x combine an 180 MHz ARM926EJ-S CPU core, High-speed USB 2.0OTG, 192 KB SRAM, NAND flash controller, flexible external bus interface, an integratedaudio codec, Li-ion charger, Real-Time Clock (RTC), and a myriad of serial and parallelinterfaces in a single chip targeted at consumer, industrial, medical, and communicationmarkets. To optimize system power consumption, the LPC315x have multiple powerdomains and a very flexible Clock Generation Unit (CGU) that provides dynamic clockgating and scaling.The LPC315x is implemented as multi-chip module with two side-by-side dies, one fordigital fuctions and one for analog functions, which include a Power Supply Unit (PSU),audio codec, RTC, and Li-ion battery charger.
上傳時間： 2014-01-17
上傳用戶：Altman
The PLB BRAM Interface Controller is a module thatattaches to the PLB (Processor Local Bus).
上傳時間： 2013-10-27
上傳用戶：Breathe0125
針對傳統(tǒng)集成電路（ASIC）功能固定、升級困難等缺點，利用FPGA實現(xiàn)了擴頻通信芯片STEL-2000A的核心功能。使用ISE提供的DDS IP核實現(xiàn)NCO模塊，在下變頻模塊調(diào)用了硬核乘法器并引入CIC濾波器進行低通濾波，給出了DQPSK解調(diào)的原理和實現(xiàn)方法，推導出一種簡便的引入?仔/4固定相移的實現(xiàn)方法。采用模塊化的設計方法使用VHDL語言編寫出源程序，在Virtex-II Pro 開發(fā)板上成功實現(xiàn)了整個系統(tǒng)。測試結果表明該系統(tǒng)正確實現(xiàn)了STEL-2000A的核心功能。 Abstract: To overcome drawbacks of ASIC such as fixed functionality and upgrade difficulty, FPGA was used to realize the core functions of STEL-2000A. This paper used the DDS IP core provided by ISE to realize the NCO module, called hard core multiplier and implemented CIC filter in the down converter, described the principle and implementation detail of the demodulation of DQPSK, and derived a simple method to introduce a fixed phase shift of ?仔/4. The VHDL source code was designed by modularity method , and the complete system was successfully implemented on Virtex-II Pro development board. Test results indicate that this system successfully realize the core function of the STEL-2000A.
上傳時間： 2013-11-19
上傳用戶：neu_liyan
The data plane of the reference design consists of a configurable multi-channel XBERT modulethat generates and checks high-speed serial data transmitted and received by the MGTs. Eachchannel in the XBERT module consists of two MGTs (MGTA and MGTB), which physicallyoccupy one MGT tile in the Virtex-4 FPGA. Each MGT has its own pattern checker, but bothMGTs in a channel share the same pattern generator. Each channel can load a differentpattern. The MGT serial rate depends on the reference clock frequency and the internal PMAdivider settings. The reference design can be scaled anywhere from one channel (two MGTs)to twelve channels (twenty-four MGTs).
上傳時間： 2013-12-25
上傳用戶：jkhjkh1982
The project KEIL_IODemo shows how to use memory allocation routines (malloc) and char I/O (printf, scanf) via a serial interface with the Keil ARM toolchain. The I/O functions are adapted for the Analog Devices ADuC7000 series using the SERIAL.C module. The example also shows the efficiency of the Keil CA ARM Compiler run-time library which is tuned for single chip systems.
標簽： KEIL_IODemo allocation routines project
上傳時間： 2013-12-08
上傳用戶：ve3344
UART I/O and Memory Allocation Example for GNU The project GNU_IODemo shows how to use memory allocation routines (malloc) and char I/O (printf, scanf) via a serial interface with the GNU toolchain. The I/O functions are adapted for the Analog Devices ADuC7000 series using the SERIAL.C module. The example also shows the efficiency of the Keil CA ARM Compiler run-time library which is tuned for single chip systems.
標簽： Allocation GNU_IODemo Example project
上傳時間： 2015-05-04
上傳用戶：Amygdala
VHDL 關于2DFFT設計程序 u scinode1 ∼ scinode9.vhd: Every SCI node RTL vhdl code. The details can be seen in the following section. u 2dfft.vhd: The top module includes these scinodes and form a 3x3 SCI Torus network, and it support these sub-modules scinode1∼ scinode9 reset and clk and global_cnt signals to synchronous the sub-modules to simplify the overall design. u proj2.wfc: VSS simulation result that is the same as the ModelSim simulation result. u Pro2_2.wfc: VSS simulation result of another test pattern can’t cause overflow situation.
標簽： scinode1 scinode details 2DFFT
上傳時間： 2014-12-02
上傳用戶：15071087253
BurchED B5-X300 Spartan2e using XC2S300e device Top level file for 6809 compatible system on a chip Designed with Xilinx XC2S300e Spartan 2+ FPGA. Implemented With BurchED B5-X300 FPGA board, B5-SRAM module, B5-CF module and B5-FPGA-CPU-IO module
標簽： compatible 300 Spartan2e BurchED
上傳時間： 2015-07-07
上傳用戶：star_in_rain
encode.v The encoder syndrome.v Syndrome generator in decoder berlekamp.v Berlekamp algorithm in decoder chien-search.v Chien search and Forney algorithm in decoder decode.v The top module of the decoder inverse.v Computes multiplication inverse of an Galois field element test-bench.v The test fixture, and some brief notes on using the modules. data-rom.v A simple data source for testing run For those intelligence-challenged who can t run verilog LGPL The license
標簽： Berlekamp berlekamp algorithm generator
上傳時間： 2014-02-16
上傳用戶：fxf126@126.com
開發(fā)工具：ads1.2 主要IC：MCU：lpc2210(NXP) LCD驅動及控制IC：s6d012(samsung) 用途：lcd驅動開發(fā)入門，s6d0129開發(fā)參考 相關資料： 電路原理圖 lcd driver guide/ tft lcd驅動原理及開發(fā)過程 lcd module document/ samsung的s6d0129的datasheet和液晶屏spec mcu document/ nxp的lpc2210中英文datasheet source code/s6d0129 driver/ 基于lpc2210平臺的無操作系統(tǒng)lcd(s6d0129)驅動源代碼 source code/s6d0129 driver with minigui/ 基于lpc2210平臺的無操作系統(tǒng)lcd(s6d0129)驅動源代碼，添加了minigui中間件，可實現(xiàn)復雜圖形及文字顯示
上傳時間： 2014-11-28
上傳用戶：ainimao
