msp-FET430P410 Demo - Timer_A Toggle P5.1, CCR0 Contmode ISR, DCO SMCLK
Description Toggle P5.1 using using software and TA_0 ISR. Toggle rate is
set at 50000 DCO/SMCLK cycles. Default DCO frequency used for TACLK.
Durring the TA_0 ISR P5.1 is toggled and 50000 clock cycles are added to CCR0. TA_0 ISR is triggered exactly 50000 cycles. CPU is normally off and
used only durring TA_ISR.
ACLK = n/a, MCLK = SMCLK = TACLK = DCO ~ 800k
標(biāo)簽：
Toggle
Description
5.1
Contmode
上傳時(shí)間：
2014-01-04
上傳用戶：gut1234567
