中文版詳情瀏覽：http://www.elecfans.com/emb/fpga/20130715324029.html Xilinx UltraScale:The Next-Generation Architecture for Your Next-Generation Architecture The Xilinx® UltraScale™ architecture delivers unprecedented levels of integration and capability with ASIC-class system- level performance for the most demanding applications. The UltraScale architecture is the industr y's f irst application of leading-edge ASIC architectural enhancements in an All Programmable architecture that scales from 20 nm planar through 16 nm FinFET technologies and beyond, in addition to scaling from monolithic through 3D ICs. Through analytical co-optimization with the X ilinx V ivado® Design Suite, the UltraScale architecture provides massive routing capacity while intelligently resolving typical bottlenecks in ways never before possible. This design synergy achieves greater than 90% utilization with no performance degradation. Some of the UltraScale architecture breakthroughs include: • Strategic placement (virtually anywhere on the die) of ASIC-like system clocks, reducing clock skew by up to 50% • Latency-producing pipelining is virtually unnecessary in systems with massively parallel bus architecture, increasing system speed and capability • Potential timing-closure problems and interconnect bottlenecks are eliminated, even in systems requiring 90% or more resource utilization • 3D IC integration makes it possible to build larger devices one process generation ahead of the current industr y standard • Greatly increased system performance, including multi-gigabit serial transceivers, I/O, and memor y bandwidth is available within even smaller system power budgets • Greatly enhanced DSP and packet handling The Xilinx UltraScale architecture opens up whole new dimensions for designers of ultra-high-capacity solutions.
標簽： UltraScale Xilinx 架構
上傳時間： 2013-11-21
上傳用戶：wxqman
Today’s digital systems combine a myriad of chips with different voltage configurations.Designers must interface 2.5V processors with 3.3V memories—both RAM and ROM—as wellas 5V buses and multiple peripheral chips. Each chip has specific power supply needs. CPLDsare ideal for handling the multi-voltage interfacing, but do require forethought to ensure correctoperation.
上傳時間： 2013-11-10
上傳用戶：yy_cn
The data plane of the reference design consists of a configurable multi-channel XBERT modulethat generates and checks high-speed serial data transmitted and received by the MGTs. Eachchannel in the XBERT module consists of two MGTs (MGTA and MGTB), which physicallyoccupy one MGT tile in the Virtex-4 FPGA. Each MGT has its own pattern checker, but bothMGTs in a channel share the same pattern generator. Each channel can load a differentpattern. The MGT serial rate depends on the reference clock frequency and the internal PMAdivider settings. The reference design can be scaled anywhere from one channel (two MGTs)to twelve channels (twenty-four MGTs).
上傳時間： 2013-12-25
上傳用戶：jkhjkh1982
ARM通訊 H-JTAG 是一款簡單易用的的調(diào)試代理軟件，功能和流行的MULTI-ICE 類似。H-JTAG 包括兩個工具軟件：H-JTAG SERVER 和H-FLASHER。其中，H-JTAG SERVER 實現(xiàn)調(diào)試代理的功能，而H-FLASHER則實現(xiàn)了FLASH 燒寫的功能。H-JTAG 的基本結構如下圖1-1所示。 H-JTAG支持所有基于ARM7 和ARM9的芯片的調(diào)試，并且支持大多數(shù)主流的ARM調(diào)試軟件，如ADS、RVDS、IAR 和KEIL。通過靈活的接口配置，H-JTAG 可以支持WIGGLER，SDT-JTAG 和用戶自定義的各種JTAG 調(diào)試小板。同時，附帶的H-FLASHER 燒寫軟件還支持常用片內(nèi)片外FLASH 的燒寫。使用H-JTAG，用戶能夠方便的搭建一個簡單易用的ARM 調(diào)試開發(fā)平臺。H-JTAG 的功能和特定總結如下： 1. 支持 RDI 1.5.0 以及 1.5.1； 2. 支持所有ARM7 以及 ARM9 芯片； 3. 支持 THUMB 以及ARM 指令； 4. 支持 LITTLE-ENDIAN 以及 BIG-ENDIAN； 5. 支持 SEMIHOSTING； 6. 支持 WIGGLER， SDT-JTAG和用戶自定義JTAG調(diào)試板； 7. 支持 WINDOWS 9.X/NT/2000/XP； 8．支持常用FLASH 芯片的編程燒寫； 9. 支持LPC2000 和AT91SAM 片內(nèi)FLASH 的自動下載；
標簽： H-JTAG 調(diào)試軟件
上傳時間： 2013-11-19
上傳用戶：水中浮云
XMail is an Internet and intranet mail server featuring an SMTP server, POP3 server, finger server, multiple domains, no need for users to have a real system account, SMTP relay checking, RBL/RSS/ORBS/DUL and custom ( IP based and address based ) spam protection, SMTP authentication ( PLAIN LOGIN CRAM-MD5 POP3-before-SMTP and custom ), a POP3 account syncronizer with external POP3 accounts, account aliases, domain aliases, custom mail processing, direct mail files delivery, custom mail filters, mailing lists, remote administration, custom mail exchangers, logging, and multi-platform code. XMail sources compile under GNU/Linux, FreeBSD, OpenBSD, NetBSD, OSX, Solaris and NT/2K/XP.
標簽： server featuring Internet intranet
上傳時間： 2015-01-12
上傳用戶：asddsd
來自《VC6.0可視化編程》的源碼，適用于初學者。 這是第一章，關于multi windows 的代碼
上傳時間： 2013-12-20
上傳用戶：TF2015
linux下的gdbserver源碼，供multi-ice調(diào)試ARM處理器
上傳時間： 2013-12-24
上傳用戶：txfyddz
The practice of enterprise application development has benefited from the emergence of many new enabling technologies. Multi-tiered object-oriented platforms, such as Java and .NET, have become commonplace.
標簽： application development enterprise benefited
上傳時間： 2015-03-11
上傳用戶：aig85
人工股市（Artificial Stock Market，簡稱ASM）是模擬股市運作的一個程序。在這個電腦中的虛擬市場中，若干被稱為交易者的人工智能程序(Agent)通過觀察它們所在的數(shù)字世界中股價和股息的不斷變換而做出預測，并且根據(jù)這些預測做出購買股票與否以及購買股票數(shù)量的決策。反過來，所有的交易者的決策又決定了股票的價格，這樣，整個的股票交易市場就構成了一個自我封閉的計算系統(tǒng)。同時，這些交易者都具有學習的能力，可以根據(jù)以前預測的成功或者失敗對自己的決策進行調(diào)整，并且通過一種被稱為遺傳算法的方法產(chǎn)生創(chuàng)新能力。
標簽： Artificial Market Stock 人工
上傳時間： 2014-01-04
上傳用戶：manlian
人工股市（Artificial Stock Market，簡稱ASM）是模擬股市運作的一個程序。在這個電腦中的虛擬市場中，若干被稱為交易者的人工智能程序(Agent)通過觀察它們所在的數(shù)字世界中股價和股息的不斷變換而做出預測，并且根據(jù)這些預測做出購買股票與否以及購買股票數(shù)量的決策。反過來，所有的交易者的決策又決定了股票的價格，這樣，整個的股票交易市場就構成了一個自我封閉的計算系統(tǒng)。同時，這些交易者都具有學習的能力，可以根據(jù)以前預測的成功或者失敗對自己的決策進行調(diào)整，并且通過一種被稱為遺傳算法的方法產(chǎn)生創(chuàng)新能力。總之，ASM是一個電腦中不斷進化的虛擬股票市場！通過研究ASM，我們可以更好的理解現(xiàn)實世界的行為，并且它提供了一個很好的現(xiàn)實股市的隱喻。 備注：該程序運行需要有Swarm平臺的支持，關于這個平臺可以到http://www.swarm.org免費下載。
標簽： Artificial Market Stock 人工
上傳時間： 2013-12-11
上傳用戶：皇族傳媒
