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通信IP網(wǎng)作為實(shí)時(shí)業(yè)務(wù)傳輸載體，要求能夠?qū)ο噜徬到y(tǒng)之間通信故障進(jìn)行快速檢測(cè)，在出現(xiàn)故障時(shí)可以快速切換到備份鏈路，以保證實(shí)時(shí)數(shù)據(jù)不間斷傳輸。在研究BFD協(xié)議原理的基礎(chǔ)上，根據(jù)通信IP網(wǎng)運(yùn)行中出現(xiàn)的問(wèn)題，應(yīng)用BFD雙向快速檢測(cè)功能，實(shí)現(xiàn)了VRRP的Master/Backup狀態(tài)毫秒級(jí)切換，并利用BFD會(huì)話檢測(cè)靜態(tài)路由所在鏈路的狀態(tài)，實(shí)現(xiàn)一跳和多跳的靜態(tài)路由自動(dòng)切換，提高了通信IP網(wǎng)的可靠性。
標(biāo)簽：
BFD
通信IP網(wǎng)
上傳時(shí)間：
2013-11-09
上傳用戶：wivai
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為提升虛擬儀器傳輸速率與實(shí)時(shí)性能，擴(kuò)展監(jiān)測(cè)范圍，在VC的軟件平臺(tái)上設(shè)計(jì)了一種全功能虛擬示波器。與傳統(tǒng)虛擬示波器相比，該系統(tǒng)采用嵌入式系統(tǒng)完成信號(hào)采集，采用工業(yè)以太網(wǎng)為傳輸介質(zhì)，通過(guò)線性插值算法和多線程編程思想，實(shí)現(xiàn)波形顯示、參數(shù)計(jì)算、頻譜分析以及波形存儲(chǔ)及回放功能。實(shí)驗(yàn)結(jié)果表明，該虛擬示波器可以實(shí)現(xiàn)20 kHz采樣頻率下的波形精確顯示，達(dá)到預(yù)期的各項(xiàng)指標(biāo)。
Abstract:
o enhance the transfer rate and real-time of virtual instrument performance， expand scope of monitoring， this paper uses the VCs software platform to design a fully functional virtual oscilloscope. Compared with traditional virtual oscilloscope， this system adopts the embedded system to complete the data acquisition， industrial Ethernet as the transmission medium used by the linear interpolation algorithm and multi-threaded programming ideas， namely to achieve waveform display， parameter calculation， spectrum analysis and waveform storage and playback. Experimental results show that the virtual oscilloscope can accurately display the waveform with 20kHz sampling frequency， and achieve the desired targets.
標(biāo)簽：
以太網(wǎng)
虛擬
波器設(shè)計(jì)
上傳時(shí)間：
2013-11-25
上傳用戶：wbwyl
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Abstract: Communication with 1-Wire slave devices requires a 1-Wire master. There are numerous ways to build a 1-Wire master (see reference design 4206, "Choosing the Right 1-Wire Master for Embedded Applications"). Thisdocument describes the DS1WM, a synthesizable 1-Wire master that can be implemented in an application-specificintegrated circuit (ASIC) or field-programmable gate array (FPGA).
標(biāo)簽：
Wire
總線
主機(jī)
上傳時(shí)間：
2014-12-22
上傳用戶：xanxuan
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The #1 Step-by-Step Guide to labviewNow Completely Updated for labview 8!
Master labview 8 with the industry's friendliest, most intuitive tutorial: labview for Everyone, Third Edition. Top labview experts Jeffrey Travis and Jim Kring teach labview the easy way: through carefully explained, step-by-step examples that give you reusable code for your own projects!
This brand-new Third Edition has been fully revamped and expanded to reflect new features and techniques introduced in labview 8. You'll find two new chapters, plus dozens of new topics, including Project Explorer, AutoTool, XML, event-driven programming, error handling, regular expressions, polymorphic VIs, timed structures, advanced reporting, and much more. Certified labview Developer (CLD) candidates will find callouts linking to key objectives on NI's newest exam, making this book a more valuable study tool than ever.
Not just what to d why to do it!
Use labview to build your own virtual workbench
Master labview's foundations: wiring, creating, editing, and debugging VIs; using controls and indicators; working with data structures; and much more
Learn the "art" and best practices of effective labview development
NEW: Streamline development with labview Express VIs
NEW: Acquire data with NI-DAQmx and the labview DAQmx VIs
NEW: Discover design patterns for error handling, control structures, state machines, queued messaging, and more
NEW: Create sophisticated user interfaces with tree and tab controls, drag and drop, subpanels, and more
Whatever your application, whatever your role, whether you've used labview or not, labview for Everyone, Third Edition is the fastest, easiest way to get the results you're after!
標(biāo)簽：
Everyone
LabVIEW
for
英文
上傳時(shí)間：
2013-10-14
上傳用戶：shawvi
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同步技術(shù)是跳頻通信系統(tǒng)的關(guān)鍵技術(shù)之一，尤其是在快速跳頻通信系統(tǒng)中，常規(guī)跳頻通信通過(guò)同步字頭攜帶相關(guān)碼的方法來(lái)實(shí)現(xiàn)同步，但對(duì)于快跳頻來(lái)說(shuō)，由于是一跳或者多跳傳輸一個(gè)調(diào)制符號(hào)，難以攜帶相關(guān)碼。對(duì)此引入雙跳頻圖案方法，提出了一種適用于快速跳頻通信系統(tǒng)的同步方案。采用短碼攜帶同步信息，克服了快速跳頻難以攜帶相關(guān)碼的困難。分析了同步性能，仿真結(jié)果表明該方案同步時(shí)間短、虛警概率低、捕獲概率高，同步性能可靠。
Abstract:
Synchronization is one of the key techniques to frequency-hopping communication system， especially in the fast frequency hopping communication system. In conventional frequency hopping communication systems， synchronization can be achieved by synchronization-head which can be used to carry the synchronization information， but for the fast frequency hopping， Because modulation symbol is transmitted by per hop or multi-hop， it is difficult to carry the correlation code. For the limitation of fast frequency hopping in carrying correlation code， a fast frequency-hopping synchronization scheme with two hopping patterns is proposed. The synchronization information is carried by short code， which overcomes the difficulty of correlation code transmission in fast frequency-hopping. The performance of the scheme is analyzed， and simulation results show that the scheme has the advantages of shorter synchronization time， lower probability of false alarm， higher probability of capture and more reliable of synchronization.
標(biāo)簽：
快速跳頻
同步技術(shù)
通信系統(tǒng)
上傳時(shí)間：
2013-11-23
上傳用戶：mpquest
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ZigBee技術(shù)是一種應(yīng)用于短距離范圍內(nèi)，低傳輸數(shù)據(jù)速率下的各種電子設(shè)備之間的無(wú)線通信技術(shù)。ZigBee名字來(lái)源于蜂群使用的賴以生存和發(fā)展的通信方式，蜜蜂通過(guò)跳ZigZag形狀的舞蹈來(lái)通知發(fā)現(xiàn)的新食物源的位置、距離和方向等信息，以此作為新一代無(wú)線通訊技術(shù)的名稱。ZigBee過(guò)去又稱為“HomeRF Lite”、“RF-EasyLink”或“FireFly”無(wú)線電技術(shù)，目前統(tǒng)一稱為ZigBee技術(shù)。 2、ZigBee技術(shù)的特點(diǎn) 自從馬可尼發(fā)明無(wú)線電以來(lái)，無(wú)線通信技術(shù)一直向著不斷提高數(shù)據(jù)速率和傳輸距離的方向發(fā)展。例如：廣域網(wǎng)范圍內(nèi)的第三代移動(dòng)通信網(wǎng)絡(luò)（3G）目的在于提供多媒體無(wú)線服務(wù)，局域網(wǎng)范圍內(nèi)的標(biāo)準(zhǔn)從IEEE802.11的1Mbit/s到IEEE802.11g的54Mbit/s的數(shù)據(jù)速率。而當(dāng)前得到廣泛研究的ZigBee技術(shù)則致力于提供一種廉價(jià)的固定、便攜或者移動(dòng)設(shè)備使用的極低復(fù)雜度、成本和功耗的低速率無(wú)線通信技術(shù)。這種無(wú)線通信技術(shù)具有如下特點(diǎn)： 功耗低：工作模式情況下，ZigBee技術(shù)傳輸速率低，傳輸數(shù)據(jù)量很小，因此信號(hào)的收發(fā)時(shí)間很短，其次在非工作模式時(shí)，ZigBee節(jié)點(diǎn)處于休眠模式。設(shè)備搜索時(shí)延一般為30ms，休眠激活時(shí)延為15ms，活動(dòng)設(shè)備信道接入時(shí)延為15ms。由于工作時(shí)間較短、收發(fā)信息功耗較低且采用了休眠模式，使得ZigBee節(jié)點(diǎn)非常省電，ZigBee節(jié)點(diǎn)的電池工作時(shí)間可以長(zhǎng)達(dá)6個(gè)月到2年左右。同時(shí)，由于電池時(shí)間取決于很多因素，例如：電池種類、容量和應(yīng)用場(chǎng)合，ZigBee技術(shù)在協(xié)議上對(duì)電池使用也作了優(yōu)化。對(duì)于典型應(yīng)用，堿性電池可以使用數(shù)年，對(duì)于某些工作時(shí)間和總時(shí)間（工作時(shí)間+休眠時(shí)間）之比小于1%的情況，電池的壽命甚至可以超過(guò)10年。 數(shù)據(jù)傳輸可靠：ZigBee的媒體接入控制層（MAC層）采用talk-when-ready的碰撞避免機(jī)制。在這種完全確認(rèn)的數(shù)據(jù)傳輸機(jī)制下，當(dāng)有數(shù)據(jù)傳送需求時(shí)則立刻傳送，發(fā)送的每個(gè)數(shù)據(jù)包都必須等待接收方的確認(rèn)信息，并進(jìn)行確認(rèn)信息回復(fù)，若沒(méi)有得到確認(rèn)信息的回復(fù)就表示發(fā)生了碰撞，將再傳一次，采用這種方法可以提高系統(tǒng)信息傳輸?shù)目煽啃浴Ｍ瑫r(shí)為需要固定帶寬的通信業(yè)務(wù)預(yù)留了專用時(shí)隙，避免了發(fā)送數(shù)據(jù)時(shí)的競(jìng)爭(zhēng)和沖突。同時(shí)ZigBee針對(duì)時(shí)延敏感的應(yīng)用做了優(yōu)化，通信時(shí)延和休眠狀態(tài)激活的時(shí)延都非常短。 網(wǎng)絡(luò)容量大：ZigBee低速率、低功耗和短距離傳輸?shù)奶攸c(diǎn)使它非常適宜支持簡(jiǎn)單器件。ZigBee定義了兩種器件：全功能器件（FFD）和簡(jiǎn)化功能器件（RFD）。對(duì)全功能器件，要求它支持所有的49個(gè)基本參數(shù)。而對(duì)簡(jiǎn)化功能器件，在最小配置時(shí)只要求它支持38個(gè)基本參數(shù)。一個(gè)全功能器件可以與簡(jiǎn)化功能器件和其他全功能器件通話，可以按3種方式工作，分別為：個(gè)域網(wǎng)協(xié)調(diào)器、協(xié)調(diào)器或器件。而簡(jiǎn)化功能器件只能與全功能器件通話，僅用于非常簡(jiǎn)單的應(yīng)用。一個(gè)ZigBee的網(wǎng)絡(luò)最多包括有255個(gè)ZigBee網(wǎng)路節(jié)點(diǎn)，其中一個(gè)是主控（Master）設(shè)備，其余則是從屬（Slave）設(shè)備。若是通過(guò)網(wǎng)絡(luò)協(xié)調(diào)器（Network Coordinator），整個(gè)網(wǎng)絡(luò)最多可以支持超過(guò)64000個(gè)ZigBee網(wǎng)路節(jié)點(diǎn)，再加上各個(gè)Network Coordinator可互相連接，整個(gè)ZigBee網(wǎng)絡(luò)節(jié)點(diǎn)的數(shù)目將十分可觀。 兼容性：ZigBee技術(shù)與現(xiàn)有的控制網(wǎng)絡(luò)標(biāo)準(zhǔn)無(wú)縫集成。通過(guò)網(wǎng)絡(luò)協(xié)調(diào)器（Coordinator）自動(dòng)建立網(wǎng)絡(luò)，采用載波偵聽/沖突檢測(cè)（CSMA-CA）方式進(jìn)行信道接入。為了可靠傳遞，還提供全握手協(xié)議。
標(biāo)簽：
zigbee
上傳時(shí)間：
2013-11-24
上傳用戶：siguazgb
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The NXP LPC315x combine an 180 MHz ARM926EJ-S CPU core, High-speed USB 2.0OTG, 192 KB SRAM, NAND flash controller, flexible external bus interface, an integratedaudio codec, Li-ion charger, Real-Time Clock (RTC), and a myriad of serial and parallelinterfaces in a single chip targeted at consumer, industrial, medical, and communicationmarkets. To optimize system power consumption, the LPC315x have multiple powerdomains and a very flexible Clock Generation Unit (CGU) that provides dynamic clockgating and scaling.The LPC315x is implemented as multi-chip module with two side-by-side dies, one fordigital fuctions and one for analog functions, which include a Power Supply Unit (PSU),audio codec, RTC, and Li-ion battery charger.
標(biāo)簽：
315x
LPC
315
ARM
上傳時(shí)間：
2014-01-17
上傳用戶：Altman
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Today in many applications such as network switches, routers, multi-computers,and processor-memory interfaces, the ability to integrate hundreds of multi-gigabit I/Os is desired to make better use of the rapidly advancing IC technology.
標(biāo)簽：
時(shí)鐘恢復(fù)
英文
上傳時(shí)間：
2013-10-30
上傳用戶：ysjing
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ARM通訊
H-JTAG 是一款簡(jiǎn)單易用的的調(diào)試代理軟件，功能和流行的MULTI-ICE 類似。H-JTAG 包括兩個(gè)工具軟件：H-JTAG SERVER 和H-FLASHER。其中，H-JTAG SERVER 實(shí)現(xiàn)調(diào)試代理的功能，而H-FLASHER則實(shí)現(xiàn)了FLASH 燒寫的功能。H-JTAG 的基本結(jié)構(gòu)如下圖1-1所示。 H-JTAG支持所有基于ARM7 和ARM9的芯片的調(diào)試，并且支持大多數(shù)主流的ARM調(diào)試軟件，如ADS、RVDS、IAR 和KEIL。通過(guò)靈活的接口配置，H-JTAG 可以支持WIGGLER，SDT-JTAG 和用戶自定義的各種JTAG 調(diào)試小板。同時(shí)，附帶的H-FLASHER 燒寫軟件還支持常用片內(nèi)片外FLASH 的燒寫。使用H-JTAG，用戶能夠方便的搭建一個(gè)簡(jiǎn)單易用的ARM 調(diào)試開發(fā)平臺(tái)。H-JTAG 的功能和特定總結(jié)如下： 1. 支持 RDI 1.5.0 以及 1.5.1； 2. 支持所有ARM7 以及 ARM9 芯片； 3. 支持 THUMB 以及ARM 指令； 4. 支持 LITTLE-ENDIAN 以及 BIG-ENDIAN； 5. 支持 SEMIHOSTING； 6. 支持 WIGGLER， SDT-JTAG和用戶自定義JTAG調(diào)試板； 7. 支持 WINDOWS 9.X/NT/2000/XP； 8．支持常用FLASH 芯片的編程燒寫； 9. 支持LPC2000 和AT91SAM 片內(nèi)FLASH 的自動(dòng)下載；
標(biāo)簽：
H-JTAG
調(diào)試軟件
上傳時(shí)間：
2014-12-01
上傳用戶：Miyuki
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中文版詳情瀏覽：http://www.elecfans.com/emb/fpga/20130715324029.html
Xilinx UltraScale:The Next-Generation Architecture for Your Next-Generation Architecture
The Xilinx® UltraScale™ architecture delivers unprecedented levels of integration and capability with ASIC-class system- level performance for the most demanding applications.
The UltraScale architecture is the industr y's f irst application of leading-edge ASIC architectural enhancements in an All Programmable architecture that scales from 20 nm planar through 16 nm FinFET technologies and beyond, in addition to scaling from monolithic through 3D ICs. Through analytical co-optimization with the X ilinx V ivado® Design Suite, the UltraScale architecture provides massive routing capacity while intelligently resolving typical bottlenecks in ways never before possible. This design synergy achieves greater than 90% utilization with no performance degradation.
Some of the UltraScale architecture breakthroughs include:
• Strategic placement (virtually anywhere on the die) of ASIC-like system clocks, reducing clock skew by up to 50%
• Latency-producing pipelining is virtually unnecessary in systems with massively parallel bus architecture, increasing system speed and capability
• Potential timing-closure problems and interconnect bottlenecks are eliminated, even in systems requiring 90% or more resource utilization
• 3D IC integration makes it possible to build larger devices one process generation ahead of the current industr y standard
• Greatly increased system performance, including multi-gigabit serial transceivers, I/O, and memor y bandwidth is available within even smaller system power budgets
• Greatly enhanced DSP and packet handling
The Xilinx UltraScale architecture opens up whole new dimensions for designers of ultra-high-capacity solutions.
標(biāo)簽：
UltraScale
Xilinx
架構(gòu)
上傳時(shí)間：
2013-11-21
上傳用戶：wxqman
