The NXP LPC315x combine an 180 MHz ARM926EJ-S CPU core, High-speed USB 2.0OTG, 192 KB SRAM, NAND flash controller, flexible external bus interface, an integratedaudio codec, Li-ion charger, Real-Time Clock (RTC), and a myriad of serial and parallelinterfaces in a single chip targeted at consumer, industrial, medical, and communicationmarkets. To optimize system power consumption, the LPC315x have multiple powerdomains and a very flexible Clock Generation Unit (CGU) that provides dynamic clockgating and scaling.The LPC315x is implemented as multi-chip module with two side-by-side dies, one fordigital fuctions and one for analog functions, which include a Power Supply Unit (PSU),audio codec, RTC, and Li-ion battery charger.
上傳時間： 2014-01-17
上傳用戶：Altman
Today in many applications such as network switches, routers, multi-computers,and processor-memory interfaces, the ability to integrate hundreds of multi-gigabit I/Os is desired to make better use of the rapidly advancing IC technology.
上傳時間： 2013-10-30
上傳用戶：ysjing
#include <reg51.h>#include <main.h>#include <interrupt.h> cs5460a應用電路(含源程序)bit code table_odd_even_bit[16]={0,1,1,0,1,0,0,1,1,0,0,1,0,1,1,0}; extern uchar rs485_timeout,pointer_buf485;extern uchar rs485_buf[MAX_485_LEN];extern uchar idata spi_buf[MAX_SPI_LEN];extern uchar pointer_send,send_len; extern uchar count_1s;//extern uint count_2min;extern uint count_10s;extern uchar oper_len,send_offset,chk_sum,send_i;extern bit flag_send_data,flag_level,flag_drdy,flag_data_ok;
上傳時間： 2014-01-24
上傳用戶：heart_2007
c#數據庫開發實例:有很多的實例，對學習非常的有意義！ 酒店管理系統源代碼 醫院信息管理系統源代碼 圖書館管理系統源代碼 財務管理系統源代碼 生產管理系統源代碼 人力資源管理實例程序源代碼 進銷存管理實例程序源代碼 if exists (select * from dbo.sysobjects where id = object_id(N'[dbo].[采購訂單_供貨商_fk]') and OBJECTPROPERTY(id, N'IsForeignKey') = 1) ALTER TABLE [dbo].[采購訂單] DROP CONSTRAINT 采購訂單_供貨商_fk GO if exists (select * from dbo.sysobjects where id = object_id(N'[dbo].[采購訂單歷史_供貨商_fk]') and OBJECTPROPERTY(id, N'IsForeignKey') = 1) ALTER TABLE [dbo].[采購訂單歷史] DROP CONSTRAINT 采購訂單歷史_供貨商_fk
上傳時間： 2013-10-30
上傳用戶：392210346
C++在幾乎所有的計算環境中都非常普及，而且可以用于幾乎所有的應用程序。C++從C中繼承了過程化編程的高效性，并集成了面向對象編程的功能。C++在其標準庫中提供了大量的功能。有許多商業C++庫支持數量眾多的操作系統環境和專業應用程序。但因為它的內容太多了，所以掌握C++并不十分容易。本書詳述了C++語言的各個方面，包括數據類型、程序控制、函數、指針、調試、類、重載、繼承、多態性、模板、異常和輸入輸出等內容。每一章都以前述內容為基礎，每個關鍵點都用具體的示例進行詳細的講解。本書基本不需要讀者具備任何C++知識，書中包含了理解C++的所有必要知識，讀者可以從頭開始編寫自己的C++程序。本書也適合于具備另一種語言編程經驗但希望全面掌握C++語言的讀者。 I created all the files under Microsoft Windows so lines are terminated by CR/LF. In addition to this "ReadMe" file you will find three zip archives in the primary archive, so you need to unzip each of these to get at the code. 為PDG格式,這有pdg閱讀器下載|pdg文件閱讀器下載
標簽： 源代碼
上傳時間： 2013-11-18
上傳用戶：gaoqinwu
一個24c16的讀寫程序（已經調試過）(arens) //////////////////////////////////////////////////////////////// //24c16讀寫驅動程序，FM24C16A-AT24C16中文資料pdf //=-------------------------------------------------------------------------------/*模塊調用:讀數據:read(unsigned int address)寫數據:write(unsigned int address,unsigned char dd) dd為要寫的 數據字節*///---------------------------------------------------------------------------------- sbit sda=P3^0;sbit scl=P3^1; sbit a0=ACC^0; //定義ACC的位，利用ACC操作速度最快sbit a1=ACC^1;sbit a2=ACC^2;sbit a3=ACC^3;sbit a4=ACC^4;sbit a5=ACC^5;sbit a6=ACC^6;sbit a7=ACC^7; //--------------------------------------------------------------------------------------#pragma disablevoid s24(void) //起始函數{_nop_(); scl=0; sda=1; scl=1; _nop_(); sda=0; _nop_(); _nop_(); scl=0; _nop_(); _nop_(); sda=1;
上傳時間： 2013-10-31
上傳用戶：fdfadfs
ARM通訊 H-JTAG 是一款簡單易用的的調試代理軟件，功能和流行的MULTI-ICE 類似。H-JTAG 包括兩個工具軟件：H-JTAG SERVER 和H-FLASHER。其中，H-JTAG SERVER 實現調試代理的功能，而H-FLASHER則實現了FLASH 燒寫的功能。H-JTAG 的基本結構如下圖1-1所示。 H-JTAG支持所有基于ARM7 和ARM9的芯片的調試，并且支持大多數主流的ARM調試軟件，如ADS、RVDS、IAR 和KEIL。通過靈活的接口配置，H-JTAG 可以支持WIGGLER，SDT-JTAG 和用戶自定義的各種JTAG 調試小板。同時，附帶的H-FLASHER 燒寫軟件還支持常用片內片外FLASH 的燒寫。使用H-JTAG，用戶能夠方便的搭建一個簡單易用的ARM 調試開發平臺。H-JTAG 的功能和特定總結如下： 1. 支持 RDI 1.5.0 以及 1.5.1； 2. 支持所有ARM7 以及 ARM9 芯片； 3. 支持 THUMB 以及ARM 指令； 4. 支持 LITTLE-ENDIAN 以及 BIG-ENDIAN； 5. 支持 SEMIHOSTING； 6. 支持 WIGGLER， SDT-JTAG和用戶自定義JTAG調試板； 7. 支持 WINDOWS 9.X/NT/2000/XP； 8．支持常用FLASH 芯片的編程燒寫； 9. 支持LPC2000 和AT91SAM 片內FLASH 的自動下載；
上傳時間： 2014-12-01
上傳用戶：Miyuki
中文版詳情瀏覽：http://www.elecfans.com/emb/fpga/20130715324029.html Xilinx UltraScale:The Next-Generation Architecture for Your Next-Generation Architecture The Xilinx® UltraScale™ architecture delivers unprecedented levels of integration and capability with ASIC-class system- level performance for the most demanding applications. The UltraScale architecture is the industr y's f irst application of leading-edge ASIC architectural enhancements in an All Programmable architecture that scales from 20 nm planar through 16 nm FinFET technologies and beyond, in addition to scaling from monolithic through 3D ICs. Through analytical co-optimization with the X ilinx V ivado® Design Suite, the UltraScale architecture provides massive routing capacity while intelligently resolving typical bottlenecks in ways never before possible. This design synergy achieves greater than 90% utilization with no performance degradation. Some of the UltraScale architecture breakthroughs include: • Strategic placement (virtually anywhere on the die) of ASIC-like system clocks, reducing clock skew by up to 50% • Latency-producing pipelining is virtually unnecessary in systems with massively parallel bus architecture, increasing system speed and capability • Potential timing-closure problems and interconnect bottlenecks are eliminated, even in systems requiring 90% or more resource utilization • 3D IC integration makes it possible to build larger devices one process generation ahead of the current industr y standard • Greatly increased system performance, including multi-gigabit serial transceivers, I/O, and memor y bandwidth is available within even smaller system power budgets • Greatly enhanced DSP and packet handling The Xilinx UltraScale architecture opens up whole new dimensions for designers of ultra-high-capacity solutions.
標簽： UltraScale Xilinx 架構
上傳時間： 2013-11-21
上傳用戶：wxqman
Today’s digital systems combine a myriad of chips with different voltage configurations.Designers must interface 2.5V processors with 3.3V memories—both RAM and ROM—as wellas 5V buses and multiple peripheral chips. Each chip has specific power supply needs. CPLDsare ideal for handling the multi-voltage interfacing, but do require forethought to ensure correctoperation.
上傳時間： 2013-11-10
上傳用戶：yy_cn
This application note provides a functional description of VHDL source code for a N x N DigitalCrosspoint Switch. The code is designed with eight inputs and eight outputs in order to targetthe 128-macrocell CoolRunner™-II CPLD device but can be easily expanded to target higherdensity devices. To obtain the VHDL source code described in this document, go to sectionVHDL Code, page 5 for instructions.
標簽： CoolRunner-II XAPP CPLD 380
上傳時間： 2013-10-26
上傳用戶：kiklkook
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