The NXP LPC315x combine an 180 MHz ARM926EJ-S CPU core, High-speed USB 2.0OTG, 192 KB SRAM, NAND flash controller, flexible external bus interface, an integratedaudio codec, Li-ion charger, Real-Time Clock (RTC), and a myriad of serial and parallelinterfaces in a single chip targeted at consumer, industrial, medical, and communicationmarkets. To optimize system power consumption, the LPC315x have multiple powerdomains and a very flexible Clock Generation Unit (CGU) that provides dynamic clockgating and scaling.The LPC315x is implemented as multi-chip module with two side-by-side dies, one fordigital fuctions and one for analog functions, which include a Power Supply Unit (PSU),audio codec, RTC, and Li-ion battery charger.
上傳時(shí)間： 2014-01-17
上傳用戶(hù)：Altman
Today in many applications such as network switches, routers, multi-computers,and processor-memory interfaces, the ability to integrate hundreds of multi-gigabit I/Os is desired to make better use of the rapidly advancing IC technology.
標(biāo)簽： 時(shí)鐘恢復(fù) 英文
上傳時(shí)間： 2013-10-30
上傳用戶(hù)：ysjing
ARM通訊 H-JTAG 是一款簡(jiǎn)單易用的的調(diào)試代理軟件，功能和流行的MULTI-ICE 類(lèi)似。H-JTAG 包括兩個(gè)工具軟件：H-JTAG SERVER 和H-FLASHER。其中，H-JTAG SERVER 實(shí)現(xiàn)調(diào)試代理的功能，而H-FLASHER則實(shí)現(xiàn)了FLASH 燒寫(xiě)的功能。H-JTAG 的基本結(jié)構(gòu)如下圖1-1所示。 H-JTAG支持所有基于ARM7 和ARM9的芯片的調(diào)試，并且支持大多數(shù)主流的ARM調(diào)試軟件，如ADS、RVDS、IAR 和KEIL。通過(guò)靈活的接口配置，H-JTAG 可以支持WIGGLER，SDT-JTAG 和用戶(hù)自定義的各種JTAG 調(diào)試小板。同時(shí)，附帶的H-FLASHER 燒寫(xiě)軟件還支持常用片內(nèi)片外FLASH 的燒寫(xiě)。使用H-JTAG，用戶(hù)能夠方便的搭建一個(gè)簡(jiǎn)單易用的ARM 調(diào)試開(kāi)發(fā)平臺(tái)。H-JTAG 的功能和特定總結(jié)如下： 1. 支持 RDI 1.5.0 以及 1.5.1； 2. 支持所有ARM7 以及 ARM9 芯片； 3. 支持 THUMB 以及ARM 指令； 4. 支持 LITTLE-ENDIAN 以及 BIG-ENDIAN； 5. 支持 SEMIHOSTING； 6. 支持 WIGGLER， SDT-JTAG和用戶(hù)自定義JTAG調(diào)試板； 7. 支持 WINDOWS 9.X/NT/2000/XP； 8．支持常用FLASH 芯片的編程燒寫(xiě)； 9. 支持LPC2000 和AT91SAM 片內(nèi)FLASH 的自動(dòng)下載；
標(biāo)簽： H-JTAG 調(diào)試軟件
上傳時(shí)間： 2014-12-01
上傳用戶(hù)：Miyuki
中文版詳情瀏覽：http://www.elecfans.com/emb/fpga/20130715324029.html Xilinx UltraScale:The Next-Generation Architecture for Your Next-Generation Architecture The Xilinx® UltraScale™ architecture delivers unprecedented levels of integration and capability with ASIC-class system- level performance for the most demanding applications. The UltraScale architecture is the industr y's f irst application of leading-edge ASIC architectural enhancements in an All Programmable architecture that scales from 20 nm planar through 16 nm FinFET technologies and beyond, in addition to scaling from monolithic through 3D ICs. Through analytical co-optimization with the X ilinx V ivado® Design Suite, the UltraScale architecture provides massive routing capacity while intelligently resolving typical bottlenecks in ways never before possible. This design synergy achieves greater than 90% utilization with no performance degradation. Some of the UltraScale architecture breakthroughs include: • Strategic placement (virtually anywhere on the die) of ASIC-like system clocks, reducing clock skew by up to 50% • Latency-producing pipelining is virtually unnecessary in systems with massively parallel bus architecture, increasing system speed and capability • Potential timing-closure problems and interconnect bottlenecks are eliminated, even in systems requiring 90% or more resource utilization • 3D IC integration makes it possible to build larger devices one process generation ahead of the current industr y standard • Greatly increased system performance, including multi-gigabit serial transceivers, I/O, and memor y bandwidth is available within even smaller system power budgets • Greatly enhanced DSP and packet handling The Xilinx UltraScale architecture opens up whole new dimensions for designers of ultra-high-capacity solutions.
標(biāo)簽： UltraScale Xilinx 架構(gòu)
上傳時(shí)間： 2013-11-21
上傳用戶(hù)：wxqman
Today’s digital systems combine a myriad of chips with different voltage configurations.Designers must interface 2.5V processors with 3.3V memories—both RAM and ROM—as wellas 5V buses and multiple peripheral chips. Each chip has specific power supply needs. CPLDsare ideal for handling the multi-voltage interfacing, but do require forethought to ensure correctoperation.
上傳時(shí)間： 2013-11-10
上傳用戶(hù)：yy_cn
This application note provides a functional description of VHDL source code for a N x N DigitalCrosspoint Switch. The code is designed with eight inputs and eight outputs in order to targetthe 128-macrocell CoolRunner™-II CPLD device but can be easily expanded to target higherdensity devices. To obtain the VHDL source code described in this document, go to sectionVHDL Code, page 5 for instructions.
標(biāo)簽： CoolRunner-II XAPP CPLD 380
上傳時(shí)間： 2013-10-26
上傳用戶(hù)：kiklkook
The Virtex-4 features, such as the programmable IDELAY and built-in FIFO support, simplifythe bridging of a high-speed, PCI-X core to large amounts of DDR-SDRAM memory. Onechallenge is meeting the PCI-X target initial latency specification. PCI-X Protocol Addendum tothe PCI Local Bus Specification Revision 2.0a ([Ref 6]) dictates that when a target signals adata transfer, "the target must do so within 16 clocks of the assertion of FRAME#." PCItermination transactions, such as Split Response/Complete, are commonly used to meet thelatency specifications. This method adds complexity to the design, as well as additional systemlatency. Another solution is to increase the ratio of the memory frequency to the PCI-X busfrequency. However, this solution increases the required power and clock resource usage.
上傳時(shí)間： 2013-11-24
上傳用戶(hù)：18707733937
UG157 - LogiCORE™ IP Initiator/Target v3.1 for PCI™ 入門(mén)指南
標(biāo)簽： Initiator LogiCORE 157 UG
上傳時(shí)間： 2013-10-13
上傳用戶(hù)：heheh
針對(duì)在xPC平臺(tái)下開(kāi)發(fā)的實(shí)時(shí)仿真系統(tǒng)依賴(lài)于MATLAB環(huán)境，影響其在工程實(shí)踐中推廣應(yīng)用的問(wèn)題，提出了一種基于xPC Target和LabWindows/CVI的實(shí)時(shí)仿真系統(tǒng)設(shè)計(jì)方法。采用該方法設(shè)計(jì)的仿真系統(tǒng)，實(shí)現(xiàn)了獨(dú)立的宿主機(jī)程序，同時(shí)利用LabWindows/CVI虛擬儀器技術(shù)開(kāi)發(fā)出了主控臺(tái)仿真軟件。經(jīng)仿真驗(yàn)證，該系統(tǒng)具備仿真步長(zhǎng)1 ms，數(shù)據(jù)通訊周期20 ms，顯示更新周期20 ms的實(shí)時(shí)仿真能力。仿真系統(tǒng)界面友好且易于操作，為xPC平臺(tái)下的實(shí)時(shí)仿真系統(tǒng)在工程實(shí)際的應(yīng)用提供了有益參考。
標(biāo)簽： xPC CVI 實(shí)時(shí)仿真系統(tǒng) 設(shè)計(jì)實(shí)現(xiàn)
上傳時(shí)間： 2013-10-10
上傳用戶(hù)：cepsypeng
The data plane of the reference design consists of a configurable multi-channel XBERT modulethat generates and checks high-speed serial data transmitted and received by the MGTs. Eachchannel in the XBERT module consists of two MGTs (MGTA and MGTB), which physicallyoccupy one MGT tile in the Virtex-4 FPGA. Each MGT has its own pattern checker, but bothMGTs in a channel share the same pattern generator. Each channel can load a differentpattern. The MGT serial rate depends on the reference clock frequency and the internal PMAdivider settings. The reference design can be scaled anywhere from one channel (two MGTs)to twelve channels (twenty-four MGTs).
標(biāo)簽： RocketIO Virtex XAPP 713
上傳時(shí)間： 2013-12-25
上傳用戶(hù)：jkhjkh1982
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