16位計數(shù)器的設(shè)計，這里是實現(xiàn)上述功能的VHDL源程序，供大家學(xué)習(xí)和討論。\r\n
上傳時間： 2013-09-05
上傳用戶：weiwolkt
cpld的入門交流：CPLD的跑馬燈一個簡易型cpld試驗電路用VHDL語言遍的
上傳時間： 2013-09-06
上傳用戶：blacklee
集中了十幾個vhdl經(jīng)典程序,如lcd,led控制程序和多種接口程序
上傳時間： 2013-09-06
上傳用戶：Huge_Brother
用VHDL語言在CPLD上實現(xiàn)串行通信
上傳時間： 2013-09-06
上傳用戶：q3290766
程序主要用硬件描述語言（VHDL）實現(xiàn)：\r\n單片機與FPGA接口通信的問題
上傳時間： 2013-09-06
上傳用戶：ddddddos
此曼徹斯特碼的解碼程序是采用VHDL硬件語言編寫的。
上傳時間： 2013-09-06
上傳用戶：zhouli
用vhdl編寫的基于fpga的數(shù)字頻率計程序算法
標(biāo)簽： vhdl fpga 編寫 數(shù)字頻率計
上傳時間： 2013-09-07
上傳用戶：chfanjiang
This document was developed under the Standard Hardware and Reliability Program (SHARP) TechnologyIndependent Representation of Electronic Products (TIREP) project. It is intended for use by VHSIC HardwareDescription Language (VHDL) design engineers and is offered as guidance for the development of VHDL modelswhich are compliant with the VHDL Data Item Description (DID DI-EGDS-80811) and which can be providedto manufacturing engineering personnel for the development of production data and the subsequent productionof hardware. Most VHDL modeling performed to date has been concentrated at either the component level orat the conceptual system level. The assembly and sub-assembly levels have been largely disregarded. Under theSHARP TIREP project, an attempt has been made to help close this gap. The TIREP models are based upon lowcomplexity Standard Electronic Modules (SEM) of the format A configuration. Although these modules are quitesimple, it is felt that the lessons learned offer guidance which can readily be applied to a wide range of assemblytypes and complexities.
標(biāo)簽： Modelling Guide Navy VHDL
上傳時間： 2014-12-23
上傳用戶：xinhaoshan2016
本文詳細討論了VHDL語句對PLD設(shè)計的影響和設(shè)計經(jīng)驗，經(jīng)典文章，值得仔細閱讀消化。,PLD Programming Using VHDL
標(biāo)簽： Programming Using VHDL PLD
上傳時間： 2013-11-17
上傳用戶：teddysha
本文簡單討論并總結(jié)了VHDL、Verilog，System verilog 這三中語言的各自特點和區(qū)別As the number of enhancements to variousHardware Description Languages (HDLs) hasincreased over the past year, so too has the complexityof determining which language is best fora particular design. Many designers and organizationsare contemplating whether they shouldswitch from one HDL to another.
標(biāo)簽： Verilog verilog System VHDL
上傳時間： 2013-10-16
上傳用戶：牛布牛
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