The government of a small but important country has decided that the alphabet needs to be streamlined and reordered. Uppercase letters will be eliminated. They will issue a royal decree in the form of a String of B and A characters. The first character in the decree specifies whether a must come ( B )Before b in the new alphabet or ( A )After b . The second character determines the relative placement of b and c , etc. So, for example, "BAA" means that a must come Before b , b must come After c , and c must come After d .
Any letters beyond these requirements are to be excluded, so if the decree specifies k comparisons then the new alphabet will contain the first k+1 lowercase letters of the current alphabet.
Create a class Alphabet that contains the method choices that takes the decree as input and returns the number of possible new alphabets that conform to the decree. If more than 1,000,000,000 are possible, return -1.
Definition
20世紀(jì)90年代中期，因使用ASIC實(shí)現(xiàn)芯片組受到啟發(fā)，萌生應(yīng)該將完整計(jì)算機(jī)所有不同的功能塊一
次直接集成于一顆硅片上的想法。這種芯片，初始起名叫System on a Chip(SoC)，直譯的中文名是
系統(tǒng)級(jí)芯片
This paper presents several low-latency mixed-timing
FIFO (first-in–first-out) interfaces designs that interface systems
on a chip working at different speeds. The connected systems
can be either synchronous or asynchronous. The designs are then
adapted to work between systems with very long interconnect
delays, by migrating a single-clock solution by Carloni et al.
(1999, 2000, and 2001) (for “l(fā)atency-insensitive” protocols) to
mixed-timing domains. The new designs can be made arbitrarily
robust with regard to metastability and interface operating speeds.
Initial simulations for both latency and throughput are promising.
數(shù)字存儲(chǔ)器和混合信號(hào)超大規(guī)模集成電路
本書系統(tǒng)地介紹了數(shù)字、存儲(chǔ)器和混合信號(hào)VLSI系統(tǒng)的測(cè)試和可測(cè)試性設(shè)計(jì)。該書是根據(jù)作者多年的科研成果和教學(xué)實(shí)踐，結(jié)合國(guó)際上關(guān)注的最新研究熱點(diǎn)并參考大量的文獻(xiàn)撰寫的。全書共分三個(gè)部分。第一部分是測(cè)試基礎(chǔ)，介紹了測(cè)試基本概念、測(cè)試設(shè)備、測(cè)試經(jīng)濟(jì)學(xué)和故障模型。第二部分是測(cè)試方法，詳細(xì)論述了組合和時(shí)序電路的測(cè)試生成、存儲(chǔ)器測(cè)試、基于DSP和基于模塊的模擬與混合信號(hào)測(cè)試、延遲測(cè)試和IDDQ測(cè)試等。第三部分是可測(cè)試性設(shè)計(jì)，包括掃描設(shè)計(jì)、BIST、邊界掃描測(cè)試、模擬測(cè)試總線標(biāo)準(zhǔn)和基于IP芯核的SOC（System on a chip）測(cè)試。
漢諾塔！！！
Simulate the movement of the Towers of Hanoi puzzle Bonus is possible for using animation
eg. if n = 2 A→B A→C B→C
if n = 3 A→C A→B C→B A→C B→A B→C A→C
