用單片機(jī)和ad0809做成的數(shù)字電壓表０～５v有原理圖，簡(jiǎn)潔易懂
標(biāo)簽： 0809 ad 用單片機(jī) 數(shù)字電壓表
上傳時(shí)間： 2013-12-13
上傳用戶(hù)：dapangxie
S-35390A是可以在超低消耗電流、寬工作電壓范圍內(nèi)工作的2線(xiàn)CMOS實(shí)時(shí)時(shí)鐘IC。工作電 壓為1.3 ~ 5.5 V、可適用于從主電源電壓到備用電池電壓的寬幅電源電壓。通過(guò)0.25 μA的計(jì) 時(shí)消耗電流和寬范圍的計(jì)時(shí)電源電壓，可大幅度地改善電池的持續(xù)時(shí)間。在使用備用電池工 作的系統(tǒng)中，內(nèi)置的自由寄存器可作為用戶(hù)備用存儲(chǔ)器來(lái)使用。在主電源切斷前存儲(chǔ)在寄存 器中的信息，可在電壓恢復(fù)后的任何時(shí)候讀出。 本產(chǎn)品因?yàn)閮?nèi)置了時(shí)鐘校正功能，所以可以在很寬的范圍內(nèi)校正因振蕩電路的頻率偏差所導(dǎo) 致的時(shí)鐘數(shù)據(jù)的提前或滯后。通過(guò)此功能和溫度傳感器的結(jié)合，可根據(jù)溫度變化來(lái)對(duì)時(shí)鐘進(jìn) 行校正，從而實(shí)現(xiàn)不受環(huán)境溫度影響的高精度的計(jì)時(shí)功能
上傳時(shí)間： 2016-10-16
上傳用戶(hù)：壞壞的華仔
// -*- Mode: Verilog -*- // Filename : wb_master.v // Description : Wishbone Master Behavorial // Author : Winefred Washington // Created On : 2002 12 24 // Last Modified By: . // Last Modified On: . // Update Count : 0 // Status : Unknown, Use with caution! // Description Specification // General Description: 8, 16, 32-bit WISHBONE Master // Supported cycles: MASTER, READ/WRITE // MASTER, BLOCK READ/WRITE // MASTER, RMW // Data port, size: 8, 16, 32-bit // Data port, granularity 8-bit // Data port, Max. operand size 32-bit // Data transfer ordering: little endian // Data transfer sequencing: undefined
標(biāo)簽： Description Behavorial wb_master Filename
上傳時(shí)間： 2014-07-11
上傳用戶(hù)：zhanditian
This diskette (version 1.0) contains demonstration programs and source codes in MATLAB (v.5.2) for algorithms listed in the textbook Global Positioning Systems, Inertial Navigation, and Integration, by M. S. Grewal, Lawrence Weill, and A. P. Andrews, published by John Wiley and Sons, 2000. Contents: MATLAB (Version 5.2) Demonstrations & Scripts Chapter4 ephemeris.m calculates the GPS satellite position in ECEF coordinates from its ephemeris parameters. Chapter5 Klobuchar_fix.m calculates the ionospheric delay. Chapter6 (shows the quaternion utilities)
標(biāo)簽： demonstration diskette contains programs
上傳時(shí)間： 2016-10-20
上傳用戶(hù)：壞天使kk
個(gè)人所得稅計(jì)算器 v個(gè)人所得稅計(jì)算器
標(biāo)簽： 計(jì)算器
上傳時(shí)間： 2014-01-23
上傳用戶(hù)：bibirnovis
Top module name : SHIFTER (File name : SHIFTER.v) 2. Input pins: SHIFT [3:0], IN [15:0], SIGN, RIGHT. 3. Output pins: OUT [15:0]. 4. Input signals generated from test pattern are latched in one cycle and are synchronized at clock rising edge. 5. The SHIFT signal describes the shift number. The shift range is 0 to 15. 6. When the signal RIGHT is high, it shifts input data to right. On the other hand, it shifts input data to left. 7. When the signal SIGN is high, the input data is a signed number and it shifts with sign extension. However, the input data is an unsigned number if the signal SIGN is low. 8. You can only use following gates in Table I and need to include the delay information (Tplh, Tphl) in your design.
標(biāo)簽： SHIFTER name module Input
上傳時(shí)間： 2013-12-13
上傳用戶(hù)：himbly
Top module name : SHIFTER (File name : SHIFTER.v) 2. Input pins: SHIFT [3:0], IN [15:0], SIGN, RIGHT. 3. Output pins: OUT [15:0]. 4. Input signals generated from test pattern are latched in one cycle and are synchronized at clock rising edge. 5. The SHIFT signal describes the shift number. The shift range is 0 to 15. 6. When the signal RIGHT is high, it shifts input data to right. On the other hand, it shifts input data to left. 7. When the signal SIGN is high, the input data is a signed number and it shifts with sign extension. However, the input data is an unsigned number if the signal SIGN is low. 8. You can only use following gates in Table I and need to include the delay information (Tplh, Tphl) in your design.
標(biāo)簽： SHIFTER name module Input
上傳時(shí)間： 2014-01-20
上傳用戶(hù)：三人用菜
代碼分為兩部分：ff_const_mul.v和ff_mul.v，從而實(shí)現(xiàn)GF乘法器，VERILOG編寫(xiě)
標(biāo)簽： ff_const_mul ff_mul 分 代碼
上傳時(shí)間： 2016-11-13
上傳用戶(hù)：
牛頓迭代法 若高階非線(xiàn)性方程組: u ( x , y) = 0 v ( x , y) = 0 可以用迭代公式
上傳時(shí)間： 2014-02-10
上傳用戶(hù)：wl9454
ram_dp_ar_aw.v 應(yīng)該蠻有用的
標(biāo)簽： ram_dp_ar_aw
上傳時(shí)間： 2013-12-03
上傳用戶(hù)：cxl274287265
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