This white paper discusses how market trends, the need for increased productivity, and new legislation have accelerated the use of safety systems in industrial machinery. This TÜV-qualified FPGA design methodology is changing the paradigms of safety designs and will greatly reduce development effort, system complexity, and time to market. This allows FPGA users to design their own customized safety controllers and provides a significant competitive advantage over traditional microcontroller or ASIC-based designs. Introduction The basic motivation of deploying functional safety systems is to ensure safe operation as well as safe behavior in cases of failure. Examples of functional safety systems include train brakes, proximity sensors for hazardous areas around machines such as fast-moving robots, and distributed control systems in process automation equipment such as those used in petrochemical plants. The International Electrotechnical Commission’s standard, IEC 61508: “Functional safety of electrical/electronic/programmable electronic safety-related systems,” is understood as the standard for designing safety systems for electrical, electronic, and programmable electronic (E/E/PE) equipment. This standard was developed in the mid-1980s and has been revised several times to cover the technical advances in various industries. In addition, derivative standards have been developed for specific markets and applications that prescribe the particular requirements on functional safety systems in these industry applications. Example applications include process automation (IEC 61511), machine automation (IEC 62061), transportation (railway EN 50128), medical (IEC 62304), automotive (ISO 26262), power generation, distribution, and transportation. 圖Figure 1. Local Safety System
上傳時間： 2013-11-14
上傳用戶：zoudejile
XAPP520將符合2.5V和3.3V I/O標準的7系列FPGA高性能I/O Bank進行連接 The I/Os in Xilinx® 7 series FPGAs are classified as either high range (HR) or high performance (HP) banks. HR I/O banks can be operated from 1.2V to 3.3V, whereas HP I/O banks are optimized for operation between 1.2V and 1.8V. In circumstances that require an HP 1.8V I/O bank to interface with 2.5V or 3.3V logic, a range of options can be deployed. This application note describes methodologies for interfacing 7 series HP I/O banks with 2.5V and 3.3V systems
上傳時間： 2013-11-06
上傳用戶：wentianyou
8051參考設計，與其他8051的免費IP相比，文檔相對較全，Oregano System 提供 This is version 1.3 of the MC8051 IP core. September 2002: Oregano Systems - Design & Consulting GesmbH Change history: - Improved tb_mc8051_siu_sim.vhd to verify duplex operation. - Corrected problem with duplex operation in file mc8051_siu_rtl.vhd
上傳時間： 2013-11-06
上傳用戶：XLHrest
a8259 可編程中斷控制 altera提供 The a8259 is designed to simplify the implementation of the interrupt interface in 8088 and 8086 based microcomputer systems. The device is known as a programmable interrupt controller. The a8259 receives and prioritizes up to 8 interrupts, and in the cascade mode, this can be expanded up to 64 interrupts. An asynchronous reset and a clock input have been added to improve operation and reliability.
上傳時間： 2015-01-02
上傳用戶：panpanpan
Full support for extended regular expressions (those with intersection and complement); Support for some kinds of cycles in grammar; DFA-based operation; Unicode support; C++ only, requires a modern compiler; Lexical analyzers can be configured to get symbols from any input class (built-in support for std::istream, std::wistream and FILE *); Designed to work with Whale, but can work standalone or interface to other parsers.
標簽： intersection expressions complement for
上傳時間： 2013-12-11
上傳用戶：zhanditian
AFD - Advanced Filter Design using MATLABMiroslav D. Lutovac, Dejan V. Tosicversion 1.00 released 15 October 1999This program is freeware.Unpack with path names, for exampleDOS: pkunzip -d afdunix: unzip -L afdAfter unpacking afd.zip, and run MATLAB,change directory to afdfrom the MATLAB command window.Execute demoafd to quickly scan the AFD operation.
標簽： D. V. MATLABMiroslav Tosicversion
上傳時間： 2015-03-21
上傳用戶：er1219
This an adaptive receiver for a direct-sequence spread spectrum (DS-SS) system over an AWGN channel. The adaptive receiver block is modified from the LMS adaptive filter block in DSP Blockset. For DS-SS signal reception, the adaptive filter needs to have multi-rate operation. The input sample rate is equal to chip rate and the output is at symbol rate. Two rates are related by PG, processing gain
標簽： direct-sequence adaptive receiver spectrum
上傳時間： 2014-01-16
上傳用戶：D&L37
This firmware translates a PS/2 mouse to a USB mouse. The translator firmware is entirely interrupt driven (with the exception of sending the data via USB to the host.) An interrupt is generated when the PS/2 start bit is received, at which time the firmware will begin its receive routine. In addition to this interrupt, every 168ms a timer overflow interrupts the main program and implements one state of the mouse state machine. This state machine handles sending bytes to and translating bytes received from the PS/2 mouse automatically. All of this is done in the background while the main program runs in the foreground. The only operation that the main program implements is sending mouse data to the PC via USB.
標簽： firmware mouse translates translator
上傳時間： 2015-04-26
上傳用戶：cuiyashuo
This m file models a DPSK UWB system using a delay in one leg of the mixer, correlation receiver low pass filter combination requiring no template for synching. Various waveforms are displayed throughout the system to allow the user to observe operation of the system.
標簽： correlation receiver models system
上傳時間： 2013-12-13
上傳用戶：semi1981
這用java語言模擬一個銀行的操作系統，main-class:run 圖形界面模式：加參數-graphic 文字模式：加參數-text Client.txt存放客戶信息 Compte.txt存放賬戶信息 operation.txt賬號使用信息 這個版本是法語版的
上傳時間： 2015-05-09
上傳用戶：hzy5825468
