To increase simulation speed, ModelSim® can apply a variety of optimizations to your design. These include, but are not limited to, mergingprocesses, pulling constants out of loops, clock suppression, and signal collapsing. You control the level of optimization by specifying certain switches when you invoke the compiler.
標簽： optimizations simulation ModelSim increase
上傳時間： 2013-12-25
上傳用戶：pkkkkp
Kiss FFT is a small and simple FFT library. It has no complicated platform-specific optimizations, can do either fixed or floating point with just a recompile, and is efficient enough for all but the most demanding applications.
標簽： platform-specific optimizations complicated FFT
上傳時間： 2016-04-07
上傳用戶：h886166
This application note covers the design considerations of a system using the performance features of the LogiCORE™ IP Advanced eXtensible Interface (AXI) Interconnect core. The design focuses on high system throughput through the AXI Interconnect core with F MAX and area optimizations in certain portions of the design. The design uses five AXI video direct memory access (VDMA) engines to simultaneously move 10 streams (five transmit video streams and five receive video streams), each in 1920 x 1080p format, 60 Hz refresh rate, and up to 32 data bits per pixel. Each VDMA is driven from a video test pattern generator (TPG) with a video timing controller (VTC) block to set up the necessary video timing signals. Data read by each AXI VDMA is sent to a common on-screen display (OSD) core capable of multiplexing or overlaying multiple video streams to a single output video stream. The output of the OSD core drives the DVI video display interface on the board. Performance monitor blocks are added to capture performance data. All 10 video streams moved by the AXI VDMA blocks are buffered through a shared DDR3 SDRAM memory and are controlled by a MicroBlaze™ processor. The reference system is targeted for the Virtex-6 XC6VLX240TFF1156-1 FPGA on the Xilinx® ML605 Rev D evaluation board
上傳時間： 2013-11-14
上傳用戶：fdmpy
This application note covers the design considerations of a system using the performance features of the LogiCORE™ IP Advanced eXtensible Interface (AXI) Interconnect core. The design focuses on high system throughput through the AXI Interconnect core with F MAX and area optimizations in certain portions of the design. The design uses five AXI video direct memory access (VDMA) engines to simultaneously move 10 streams (five transmit video streams and five receive video streams), each in 1920 x 1080p format, 60 Hz refresh rate, and up to 32 data bits per pixel. Each VDMA is driven from a video test pattern generator (TPG) with a video timing controller (VTC) block to set up the necessary video timing signals. Data read by each AXI VDMA is sent to a common on-screen display (OSD) core capable of multiplexing or overlaying multiple video streams to a single output video stream. The output of the OSD core drives the DVI video display interface on the board. Performance monitor blocks are added to capture performance data. All 10 video streams moved by the AXI VDMA blocks are buffered through a shared DDR3 SDRAM memory and are controlled by a MicroBlaze™ processor. The reference system is targeted for the Virtex-6 XC6VLX240TFF1156-1 FPGA on the Xilinx® ML605 Rev D evaluation board
上傳時間： 2013-11-23
上傳用戶：shen_dafa
The AVRcam source files were built using the WinAVR distribution (version 3.3.1 of GCC). I haven t tested other versions of GCC, but they should compile without too much difficulty. * The source files for the AVRcam had the author name and copyright information added back into them after the judging of the project, since it states in the competition rules that the author s name can not be present during their inspection. * The included source files are the ones that were submitted for the entry into the Circuit Cellar contest. I have continued to develop the AVRcam, and have added several new features (such as ignoring objects that aren t larger than a minimum size, removing tracked objects that overlap with each, and some general optimizations). If you are interested in the latest source, email me at john@jrobot.net * For more info about the AVRcam, check out http://www.jrobot.net John Orlando August 20, 2004
標簽： distribution version AVRcam source
上傳時間： 2016-12-30
上傳用戶：GavinNeko
Aircrack-ng is an 802.11 WEP and WPA-PSK keys cracking program that can recover keys once enough data packets have been captured. It implements the standard FMS attack along with some optimizations like KoreK attacks, as well as the all-new PTW attack, thus making the attack much faster compared to other WEP cracking tools. In fact, Aircrack-ng is a set of tools for auditing wireless networks.
標簽： keys Aircrack-ng cracking WPA-PSK
上傳時間： 2013-12-25
上傳用戶：bruce
The contemporary view of the Smart City is very much static and infrastructure- centric, focusing on installation and subsequent management of Edge devices and analytics of data provided by these devices. While this still allows a more efficient management of the city’s infrastructure, optimizations and savings in different do- mains, the existing architectures are currently designed as single-purpose, vertically siloed solutions. This hinders active involvement of a variety of stakeholders (e.g., citizens and businesses) who naturally form part of the city’s ecosystem and have an inherent interest in jointly coordinating and influencing city-level activities.
標簽： Internet Systems Cities People Things Smart The and of
上傳時間： 2020-05-26
上傳用戶：shancjb
