<li id="mkiao"></li> The LTC3546 is a dual output current mode buck regulatorwith fl exible output current partitioning. Beyondthe advantages normally associated with dual outputregulators (reduced size, cost, EMI and part count, withimproved effi ciency), the LTC3546’s outputs can bepartitioned for either 3A and 1A outputs, or two 2A outputs.This increases its application range and simplifi esmultiple supply rail designs. A confi gurable Burst Mode®clamp for each output sets the current transition levelbetween Burst Mode operation and forced continuousconduction mode to optimize effi ciency over the entireoutput range. An adjustable switching frequency up to4MHz and internal power MOSFET switches allow forsmall and compact footprints.
上傳時間： 2013-11-04
上傳用戶：yxgi5
NXP Semiconductor designed the LPC2400 microcontrollers around a 16-bit/32-bitARM7TDMI-S CPU core with real-time debug interfaces that include both JTAG andembedded Trace. The LPC2400 microcontrollers have 512 kB of on-chip high-speedFlash memory. This Flash memory includes a special 128-bit wide memory interface andaccelerator architecture that enables the CPU to execute sequential instructions fromFlash memory at the maximum 72 MHz system clock rate. This feature is available onlyon the LPC2000 ARM Microcontroller family of products. The LPC2400 can execute both32-bit ARM and 16-bit Thumb instructions. Support for the two Instruction Sets meansEngineers can choose to optimize their application for either performance or code size atthe sub-routine level. When the core executes instructions in Thumb state it can reducecode size by more than 30 % with only a small loss in performance while executinginstructions in ARM state maximizes core performance.
上傳時間： 2013-11-15
上傳用戶：zouxinwang
With the Altera Nios II embedded processor, you as the system designercan accelerate time-critical software algorithms by adding custominstructions to the Nios II processor instruction set. Using custominstructions, you can reduce a complex sequence of standard instructionsto a single instruction implemented in hardware. You can use this featurefor a variety of applications, for example, to optimize software innerloops for digital signal processing (DSP), packet header processing, andcomputation-intensive applications. The Nios II configuration wizard,part of the Quartus® II software’s SOPC Builder, provides a graphicaluser interface (GUI) used to add up to 256 custom instructions to theNios II processor
上傳時間： 2013-11-07
上傳用戶：swing
The NXP LPC314x combine a 270 MHz ARM926EJ-S CPU core, High-speed USB 2.0OTG, 192 KB SRAM, NAND flash controller, flexible external bus interface, three channel10-bit A/D, and a myriad of serial and parallel interfaces in a single chip targeted atconsumer, industrial, medical, and communication markets. To optimize system powerconsumption, the LPC314x have multiple power domains and a very flexible ClockGeneration Unit (CGU) that provides dynamic clock gating and scaling.
上傳時間： 2013-10-11
上傳用戶：yuchunhai1990
The NXP LPC315x combine an 180 MHz ARM926EJ-S CPU core, High-speed USB 2.0OTG, 192 KB SRAM, NAND flash controller, flexible external bus interface, an integratedaudio codec, Li-ion charger, Real-Time Clock (RTC), and a myriad of serial and parallelinterfaces in a single chip targeted at consumer, industrial, medical, and communicationmarkets. To optimize system power consumption, the LPC315x have multiple powerdomains and a very flexible Clock Generation Unit (CGU) that provides dynamic clockgating and scaling.The LPC315x is implemented as multi-chip module with two side-by-side dies, one fordigital fuctions and one for analog functions, which include a Power Supply Unit (PSU),audio codec, RTC, and Li-ion battery charger.
上傳時間： 2014-01-17
上傳用戶：Altman
Nios II定制指令用戶指南：With the Altera Nios II embedded processor, you as the system designer can accelerate time-critical software algorithms by adding custom instructions to the Nios II processor instruction set. Using custom instructions, you can reduce a complex sequence of standard instructions to a single instruction implemented in hardware. You can use this feature for a variety of applications, for example, to optimize software inner loops for digital signal processing (DSP), packet header processing, and computation-intensive applications. The Nios II configuration wizard,part of the Quartus® II software’s SOPC Builder, provides a graphical user interface (GUI) used to add up to 256 custom instructions to the Nios II processor. The custom instruction logic connects directly to the Nios II arithmetic logic unit (ALU) as shown in Figure 1–1.
上傳時間： 2013-10-12
上傳用戶：kang1923
One of the strengths of Synplify is the Finite State Machine compiler. This is a powerfulfeature that not only has the ability to automatically detect state machines in the sourcecode, and implement them with either sequential, gray, or one-hot encoding. But alsoperform a reachability analysis to determine all the states that could possibly bereached, and optimize away all states and transition logic that can not be reached.Thus, producing a highly optimal final implementation of the state machine.
標(biāo)簽： Synplicity Machine Verilog Design
上傳時間： 2013-10-20
上傳用戶：蒼山觀海
Finite state machines are widely used in digital circuit designs. Generally, when designing a state machine using an HDL, the synthesis tools will optimize away all states that cannot be reached and generate a highly optimized circuit. Sometimes, however, the optimization is not acceptable. For example, if the circuit powers up in an invalid state, or the circuit is in an extreme working environment and a glitch sends it into an undesired state, the circuit may never get back to its normal operating condition.
標(biāo)簽： Creating Machines Mentor State
上傳時間： 2013-11-02
上傳用戶：xauthu
The EM algorithm is short for Expectation-Maximization algorithm. It is based on an iterative optimization of the centers and widths of the kernels. The aim is to optimize the likelihood that the given data points are generated by a mixture of Gaussians. The numbers next to the Gaussians give the relative importance (amplitude) of each component.
標(biāo)簽： algorithm Expectation-Maximization iterative optimi
上傳時間： 2015-06-17
上傳用戶：獨(dú)孤求源
使用pso求最小化一函數(shù) matlab程式碼，寫的非常簡潔(不到100行)，且還包括了2維的圖形展示，和大家分享參考!!! 一起學(xué)習(xí)matlab和各種optimize methods 最小化：(x-15)^2+(y-20)^2 The swarm matrix is swarm(index, [location, velocity, best position, best value], [x, y components or the value component]) Author: Wesam ELSHAMY (wesamelshamy@yahoo.com) MSc Student, Electrical Enginering Dept., Faculty of Engineering Cairo University, Egypt
上傳時間： 2013-12-18
上傳用戶：zhaiye
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