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pipeline

  • 基于FPGA的FFT數字處理器的硬件實現

    DFT(Discrete Fourier Transformation)是數字信號分析與處理如圖形、語音及圖像等領域的重要變換工具,直接計算DFT的計算量與變換區間長度N的平方成正比.當N較大時,因計算量太大,直接用DFT算法進行譜分析和喜好的實時處理是不切實際的.快速傅里葉變換(Fast Fourier Transformation,簡稱FFT)使DFT運算效率提高1~2個數量級.本文的目的就是研究如何應用FPGA這種大規模可編程邏輯器件實現FFT的算法.本設計主要采用先進的基-4DIT算法研制一個具有實用價值的FFT實時硬件處理器.在FFT實時硬件處理器的設計實現過程中,利用遞歸結構以及成組浮點制運算方式,解決了蝶形計算、數據傳輸和存儲操作協調一致問題.合理地解決了位增長問題.同時,采用并行高密度乘法器和流水線(pipeline)工作方式,并將雙端口RAM、只讀ROM全部內置在FPGA芯片內部,使整個系統的數據交換和處理速度得以很大提高,實際合理地解決了資源和速度之間相互制約的問題.本設計采用Verilog HDL硬件描述語言進行設計,由于在設計中采用Xilinx公司提供的稱為Core的IP功能塊極大地提高了設計效率.

    標簽: FPGA FFT 數字處理器 硬件實現

    上傳時間: 2013-06-20

    上傳用戶:小碼農lz

  • 關于FPGA流水線設計的論文

    關于FPGA流水線設計的論文\r\nThis work investigates the use of very deep pipelines for\r\nimplementing circuits in FPGAs, where each pipeline\r\nstage is limited to a single FPGA logic element (LE). The\r\narchitecture and VHDL design of a parameterized integer\r\na

    標簽: FPGA 流水線 論文

    上傳時間: 2013-09-03

    上傳用戶:wl9454

  • CMOS_pipeline_ADC的分析與設計

    關于pipeline ADC設計的經典碩士論文

    標簽: CMOS_pipeline_ADC

    上傳時間: 2013-10-16

    上傳用戶:dingdingcandy

  • 14位pipeline ADC設計的帶隙電壓基準源技術

    關于pineline ADC的設計文獻

    標簽: pipeline ADC 帶隙 電壓基準源

    上傳時間: 2013-11-24

    上傳用戶:iven

  • 流水線ADC的行為級仿真

    行為級仿真是提高流水線(pipeline)ADC設計效率的重要手段。建立精確的行為級模型是進行行為級仿真的關鍵。本文采用基于電路宏模型技術的運算放大器模型,構建了流水線ADC的行為級模型并進行仿真。為驗證提出模型的精度,以一個7位流水線ADC為例,分別進行了電路級與行為級的仿真,并做了對比。結果表明這樣構建的行為級模型能較好地反映實際電路的特性,同時仿真時間大大縮短。

    標簽: ADC 流水線 仿真

    上傳時間: 2013-10-18

    上傳用戶:zsjinju

  • ADC轉換器技術用語 (A/D Converter Defi

    ANALOG INPUT BANDWIDTH is a measure of the frequencyat which the reconstructed output fundamental drops3 dB below its low frequency value for a full scale input. Thetest is performed with fIN equal to 100 kHz plus integer multiplesof fCLK. The input frequency at which the output is −3dB relative to the low frequency input signal is the full powerbandwidth.APERTURE JITTER is the variation in aperture delay fromsample to sample. Aperture jitter shows up as input noise.APERTURE DELAY See Sampling Delay.BOTTOM OFFSET is the difference between the input voltagethat just causes the output code to transition to the firstcode and the negative reference voltage. Bottom Offset isdefined as EOB = VZT–VRB, where VZT is the first code transitioninput voltage and VRB is the lower reference voltage.Note that this is different from the normal Zero Scale Error.CONVERSION LATENCY See pipeline DELAY.CONVERSION TIME is the time required for a completemeasurement by an analog-to-digital converter. Since theConversion Time does not include acquisition time, multiplexerset up time, or other elements of a complete conversioncycle, the conversion time may be less than theThroughput Time.DC COMMON-MODE ERROR is a specification which appliesto ADCs with differential inputs. It is the change in theoutput code that occurs when the analog voltages on the twoinputs are changed by an equal amount. It is usually expressed in LSBs.

    標簽: Converter Defi ADC 轉換器

    上傳時間: 2013-11-12

    上傳用戶:pans0ul

  • 基于C8051F930的管道溫度壓力遠程監測系統

       為解決輸油管道溫度壓力參數實時監測的問題,設計了以C8051F930單片機作為控制核心的超低功耗輸油管道溫度壓力遠程監測系統。現場儀表使用高精度電橋采集數據,通過433 MHz短距離無線通信網絡與遠程終端RTU進行通信,RTU通過GPRS網絡與PC上位機進行遠程數據傳輸,在上位機中實現數據存儲和圖形化界面顯示,從而實現輸油管道溫度壓力參數的實時監測和異常報警。經實驗證明,該系統的12位數據采集精度滿足設計要求,漏碼率小于1%,正常工作時間超過5個月,能實時有效地監測輸油管道的溫度壓力參數,節省大量人工成本,有效預防管道參數異常造成的經濟損失和環境污染。 Abstract:  In order to solve the problems on real-time monitoring of pipeline temperature and pressure parameters, the ultra-low power remote pipeline temperature and pressure monitoring system was designed by using the single chip processor C8051F930 as the control core. The high-precision electric bridge was used in field instruments for data collection, the 433MHz short-range wireless communication network was used to make communication between field instrument and RTU, the GPRS was used by the RTU to transmit data to the PC host computer, and the data was stored and displayed in the PC host computer, so the real-time monitoring and exception alerts of pipeline temperature and pressure parameters were achieved. The experiment proves that the system of which error rate is less than 1% over five months working with the 12-bit data acquisition accuracy can effectively monitor the pipeline temperature and pressure parameters in real time, it saves a lot of labor costs and effectively prevents environmental pollution and economic losses caused by abnormal channel parameters.

    標簽: C8051F930 溫度 壓力 遠程監測系統

    上傳時間: 2013-11-07

    上傳用戶:cuibaigao

  • 一種8位單片機中ALU的改進設計

    文章提出了一種精簡指令集8 位單片機中, 算術邏輯單元的工作原理。在此基礎上, 對比傳統PIC 方案、以及在ALU 內部再次采用流水線作業的332 方案、44 方案, 并用Synopsys 綜合工具實現了它們。綜合及仿真結果表明, 根據該單片機系統要求, 44 方案速度最高, 比332 方案可提高43.9%, 而面積僅比最小的332 方案增加1.6%。在分析性能差異的根本原因之后, 闡明了該方案的優越性。關鍵詞: 單片機, 精簡指令集, 算術邏輯單元, 流水線 Abstract: Work principle for ALU in an 8_bit RISC Singlechip microcomputer is described. The traditional PIC scheme, 332 pipeline scheme and 44 pipeline scheme are compared on the base of the principle, which are implemented using Synopsys design tools. Results from synthesis and simulation shows that 44 scheme operates the fast, which is 43.9% faster and only 1.6% larger than 332 scheme. The essential reason why the performance is so different is analyzed.Then the advantage of 44 scheme is clarified.Key words: Singlechip, Microcomputer, RISC, ALU, pipeline

    標簽: ALU 8位單片機

    上傳時間: 2013-10-18

    上傳用戶:xiaoyaa

  • ARM系列處理器體系結構與指令系統詳解

        常用的嵌入式處理器有ARM、MIPS、PowerPC、X86、68K/Cold fire等,MIPS是Microprocessor without Inter-locked pipeline Stages的縮寫,是由MIPS技術公司開發的一種處理器內核標準。目前有32位和64位MIPS芯片。PowerPC是早期Motorola公司和IBM公司聯合為Apple公司的MAC機開發的CPU芯片,商標權同時屬于IBM和Motorola兩家公司,并一度成為他們的主導產品。X86系列處理器起源于Intel架構的8080,然后發展出286、386、486直到現在的奔騰處理器乃至雙核處理器等。從嵌入式市場來看,486DX也應該是和ARM、68K、MIPS和SuperH齊名的5大嵌入式處理器之一。Motorola 68K是出現比較早的一款嵌入式處理器,采用的是CISC結構。  

    標簽: ARM 列處理器 指令系統

    上傳時間: 2013-10-22

    上傳用戶:dddddd55

  • LPC1850 Cortex-M3內核微控制器數據手冊

    The LPC1850/30/20/10 are ARM Cortex-M3 based microcontrollers for embeddedapplications. The ARM Cortex-M3 is a next generation core that offers systemenhancements such as low power consumption, enhanced debug features, and a highlevel of support block integration.The LPC1850/30/20/10 operate at CPU frequencies of up to 150 MHz. The ARMCortex-M3 CPU incorporates a 3-stage pipeline and uses a Harvard architecture withseparate local instruction and data buses as well as a third bus for peripherals. The ARMCortex-M3 CPU also includes an internal prefetch unit that supports speculativebranching.The LPC1850/30/20/10 include up to 200 kB of on-chip SRAM data memory, a quad SPIFlash Interface (SPIFI), a State Configuration Timer (SCT) subsystem, two High-speedUSB controllers, Ethernet, LCD, an external memory controller, and multiple digital andanalog peripherals.

    標簽: Cortex-M 1850 LPC 內核微控制器

    上傳時間: 2014-12-31

    上傳用戶:zhuoying119

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