基于單片機的住宅電子服務系統
上傳時間： 2013-10-27
上傳用戶：yanyueshen
單片機通訊電路的抗干擾設計
上傳時間： 2013-12-20
上傳用戶：jing911003
MPLAB C30用戶指南(英文) HIGHLIGHTSThe information covered in this chapter is as follows:• About this Guide• Recommended Reading• Troubleshooting• The Microchip Web Site• Development Systems Customer Notification Service• Customer Support Document LayoutThe document layout is as follows:• Chapter 1: Compiler Overview – describes MPLAB C30, development tools andfeature set.• Chapter 2: Differences between MPLAB C30 and ANSI C – describes thedifferences between the C language supported by MPLAB C30 syntax and thestandard ANSI-89 C.• Chapter 3: Using MPLAB C30 – describes how to use the MPLAB C30 compilerfrom the command line.• Chapter 4: MPLAB C30 Runtime Environment – describes the MPLAB C30runtime model, including information on sections, initialization, memory models, thesoftware stack and much more.• Chapter 5: Data Types – describes MPLAB C30 integer, floating point and pointerdata types.• Chapter 6: Device Support Files – describes the MPLAB C30 header and registerdefinition files, as well as how to use with SFR’s.• Chapter 7: Interrupts – describes how to use interrupts.• Chapter 8: Mixing Assembly Language and C Modules – provides guidelines tousing MPLAB C30 with MPLAB ASM30 assembly language modules.
上傳時間： 2013-10-21
上傳用戶：13925096126
ST 公司的STM32TS60 是集成了I2C,SPI,UART 和USB 接口的數字電阻型多觸摸屏控制器, 能同時跟蹤多達10 個單獨的觸摸,分辨率達0.17mm,觸摸屏掃描速率達125 Hz 到 250 Hz, 主要用于游戲機,智能手機,PMP,PND,MID 和筆記本電腦.本文介紹STM32TS60 主要特 性,2.5”-6”屏單器件應用電路。
上傳時間： 2013-10-21
上傳用戶：dingdingcandy
摘要：介紹了一種利用CPLD芯片設計的數字鐘電路，該系統采用自頂向下的層次模塊化 設計手段構建電路，代表了BDA的發展趨勢。文中結合實例詳盡介紹了原理圖設計輸入方 式以及設計過程。
上傳時間： 2013-11-12
上傳用戶：emhx1990
3 FPGA設計流程 完整的FPGA 設計流程包括邏輯電路設計輸入、功能仿真、綜合及時序分析、實現、加載配置、調試。FPGA 配置就是將特定的應用程序設計按FPGA設計流程轉化為數據位流加載到FPGA 的內部存儲器中，實現特定邏輯功能的過程。由于FPGA 電路的內部存儲器都是基于RAM 工藝的，所以當FPGA電路電源掉電后，內部存儲器中已加載的位流數據將隨之丟失。所以，通常將設計完成的FPGA 位流數據存于外部存儲器中，每次上電自動進行FPGA電路配置加載。 4 FPGA配置原理 以Xilinx公司的Qpro Virtex Hi-Rel系列XQV100電路為例，FPGA的配置模式有四種方案可選擇：MasterSerial Mode，Slave Serial Mode，Master selectMAPMode，Slave selectMAP Mode。配置是通過芯片上的一組專/ 復用引腳信號完成的，主要配置功能信號如下： (1)M0、M1、M2：下載配置模式選擇; (2)CLK：配置時鐘信號; (3)DONE：顯示配置狀態、控制器件啟動;
上傳時間： 2013-11-18
上傳用戶：oojj
摘要：介紹了一種利用CPLD芯片設計的數字鐘電路，該系統采用自頂向下的層次模塊化 設計手段構建電路，代表了BDA的發展趨勢。文中結合實例詳盡介紹了原理圖設計輸入方 式以及設計過程。
上傳時間： 2013-10-09
上傳用戶：15736969615
This document provides practical, common guidelines for incorporating PCI Express interconnect layouts onto Printed Circuit Boards (PCB) ranging from 4-layer desktop baseboard designs to 10- layer or more server baseboard designs. Guidelines and constraints in this document are intended for use on both baseboard and add-in card PCB designs. This includes interconnects between PCI Express devices located on the same baseboard (chip-to-chip routing) and interconnects between a PCI Express device located “down” on the baseboard and a device located “up” on an add-in card attached through a connector. This document is intended to cover all major components of the physical interconnect including design guidelines for the PCB traces, vias and AC coupling capacitors, as well as add-in card edge-finger and connector considerations. The intent of the guidelines and examples is to help ensure that good high-speed signal design practices are used and that the timing/jitter and loss/attenuation budgets can also be met from end-to-end across the PCI Express interconnect. However, while general physical guidelines and suggestions are given, they may not necessarily guarantee adequate performance of the interconnect for all layouts and implementations. Therefore, designers should consider modeling and simulation of the interconnect in order to ensure compliance to all applicable specifications. The document is composed of two main sections. The first section provides an overview of general topology and interconnect guidelines. The second section concentrates on physical layout constraints where bulleted items at the beginning of a topic highlight important constraints, while the narrative that follows offers additional insight.
上傳時間： 2014-01-24
上傳用戶：s363994250
Modern C++ Design 一書中實現的程序庫，全面體現Policy Based Programming 的靈活，提供了諸多設計模式何smart pointer的靈活實現，強烈推薦！
上傳時間： 2014-01-02
上傳用戶：libinxny
啥也不說了，請看代碼示例 File : fat_dir.c FS_DIR *FS__fat_opendir(const char *pDirName, FS_DIR *pDir) { FS_size_t len FS_u32 unit FS_u32 dstart ....... FS_u32 dsize FS_i32 i char realname[12] char *filename if (!pDir) { return 0 /* No valid pointer to a FS_DIR structure */ }
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上傳時間： 2013-12-14
上傳用戶：梧桐
