The main objective of this book is to present all the relevant informationrequired for RF and micro-wave power amplifier design includingwell-known and novel theoretical approaches and practical design techniquesas well as to suggest optimum design approaches effectively combininganalytical calculations and computer-aided design. This bookcan also be very useful for lecturing to promote the analytical way ofthinking with practical verification by making a bridge between theoryand practice of RF and microwave engineering. As it often happens, anew result is the well-forgotten old one. Therefore, the demonstrationof not only new results based on new technologies or circuit schematicsis given, but some sufficiently old ideas or approaches are also introduced,that could be very useful in modern practice or could contributeto appearance of new ideas or schematic techniques.
標(biāo)簽： Amplifier Microwave Design Power
上傳時間： 2013-12-22
上傳用戶：vodssv
針對UHF讀寫器設(shè)計中，在符合EPC Gen2標(biāo)準(zhǔn)的情況下，對標(biāo)簽返回的高速數(shù)據(jù)進行正確解碼以達到正確讀取標(biāo)簽的要求，提出了一種新的在ARM平臺下采用邊沿捕獲統(tǒng)計定時器數(shù)判斷數(shù)據(jù)的方法，并對FM0編碼進行解碼。與傳統(tǒng)的使用定時器定時采樣高低電平的FM0解碼方法相比，該解碼方法可以減少定時器定時誤差累積的影響；可以將捕獲定時器數(shù)中斷與數(shù)據(jù)判斷解碼相對分隔開，使得中斷對解碼影響很小，實現(xiàn)捕獲與解碼的同步。通過實驗表明，這種方法提高了解碼的效率，在160 Kb/s的接收速度下，讀取一張標(biāo)簽的時間約為30次/s。 Abstract: Aiming at the requirement of receiving correctly decoded data from the tag under high-speed communication which complied with EPC Gen2 standard in the design of UHF interrogator， the article introduced a new technology for FM0 decoding which counted the timer counter to judge data by using the edge interval of signal capture based on the ARM7 platform. Compared with the traditional FM0 decoding method which used the timer timed to sample the high and low level， the method could reduce the accumulation of timing error and could relatively separate capture timer interrupt and the data judgment for decoding， so that the disruption effect on the decoding was small and realizd synchronization of capture and decoding. Testing result shows that the method improves the efficiency of decoding， at 160 Kb/s receiving speed， the time of the interrogator to read a tag is about 30 times/s.
標(biāo)簽： UHF FM0 讀寫器 解碼技術(shù)
上傳時間： 2013-11-10
上傳用戶：liufei
The information in this specification is subject to change without notice.Use of this specification for product design requires an executed license agreement from the CompactFlashAssociation.The CompactFlash Association shall not be liable for technical or editorial errors or omissions contained herein; norfor incidental or consequential damages resulting from the furnishing, performance, or use of this material.All parts of the CompactFlash Specification are protected by copyright law and all rights are reserved. Thisdocumentation may not, in whole or in part, be copied, photocopied, reproduced, translated, or reduced to anyelectronic medium or machine readable form without prior consent, in writing, from the CompactFlash Association.The CFA logo is a trademark of the CompactFlash Association.Product names mentioned herein are for identification purposes only and may be trademarks and/or registeredtrademarks of their respective companies.© 1998-99, CompactFlash Association. All rights reserved.
標(biāo)簽： 技術(shù)資料
上傳時間： 2013-10-08
上傳用戶：stewart·
一個24c16的讀寫程序（已經(jīng)調(diào)試過）(arens) //////////////////////////////////////////////////////////////// //24c16讀寫驅(qū)動程序，F(xiàn)M24C16A-AT24C16中文資料pdf //=-------------------------------------------------------------------------------/*模塊調(diào)用:讀數(shù)據(jù):read(unsigned int address)寫數(shù)據(jù):write(unsigned int address,unsigned char dd) dd為要寫的 數(shù)據(jù)字節(jié)*///---------------------------------------------------------------------------------- sbit sda=P3^0;sbit scl=P3^1; sbit a0=ACC^0; //定義ACC的位，利用ACC操作速度最快sbit a1=ACC^1;sbit a2=ACC^2;sbit a3=ACC^3;sbit a4=ACC^4;sbit a5=ACC^5;sbit a6=ACC^6;sbit a7=ACC^7; //--------------------------------------------------------------------------------------#pragma disablevoid s24(void) //起始函數(shù){_nop_(); scl=0; sda=1; scl=1; _nop_(); sda=0; _nop_(); _nop_(); scl=0; _nop_(); _nop_(); sda=1;
上傳時間： 2013-10-31
上傳用戶：fdfadfs
ExpressPCB 是一款免費的PCB設(shè)計軟件，簡單實使。可以畫雙層板。 Our Free PCB software is a snap to learn and use. For the first time, designing circuit boards is simple for the beginner and efficient for the professional. Our board manufacturing service makes top quality two and four layer PCBs. Use our MiniBoard service and pay only $51 for three boards (plus $8 shipping).
標(biāo)簽： ExpressPCB PCB 設(shè)計軟件
上傳時間： 2013-11-15
上傳用戶：lchjng
ExpressPCB 是一款免費的PCB設(shè)計軟件，簡單實使。可以畫雙層板。 Our Free PCB software is a snap to learn and use. For the first time, designing circuit boards is simple for the beginner and efficient for the professional. Our board manufacturing service makes top quality two and four layer PCBs. Use our MiniBoard service and pay only $51 for three boards (plus $8 shipping).
標(biāo)簽： ExpressPCB PCB 設(shè)計軟件
上傳時間： 2013-10-09
上傳用戶：1047385479
This application note covers the design considerations of a system using the performance features of the LogiCORE™ IP Advanced eXtensible Interface (AXI) Interconnect core. The design focuses on high system throughput through the AXI Interconnect core with F MAX and area optimizations in certain portions of the design. The design uses five AXI video direct memory access (VDMA) engines to simultaneously move 10 streams (five transmit video streams and five receive video streams), each in 1920 x 1080p format, 60 Hz refresh rate, and up to 32 data bits per pixel. Each VDMA is driven from a video test pattern generator (TPG) with a video timing controller (VTC) block to set up the necessary video timing signals. Data read by each AXI VDMA is sent to a common on-screen display (OSD) core capable of multiplexing or overlaying multiple video streams to a single output video stream. The output of the OSD core drives the DVI video display interface on the board. Performance monitor blocks are added to capture performance data. All 10 video streams moved by the AXI VDMA blocks are buffered through a shared DDR3 SDRAM memory and are controlled by a MicroBlaze™ processor. The reference system is targeted for the Virtex-6 XC6VLX240TFF1156-1 FPGA on the Xilinx® ML605 Rev D evaluation board
標(biāo)簽： XAPP 740 AXI 互聯(lián)
上傳時間： 2013-11-23
上傳用戶：shen_dafa
One of the strengths of Synplify is the Finite State Machine compiler. This is a powerfulfeature that not only has the ability to automatically detect state machines in the sourcecode, and implement them with either sequential, gray, or one-hot encoding. But alsoperform a reachability analysis to determine all the states that could possibly bereached, and optimize away all states and transition logic that can not be reached.Thus, producing a highly optimal final implementation of the state machine.
標(biāo)簽： Synplicity Machine Verilog Design
上傳時間： 2013-10-20
上傳用戶：蒼山觀海
UART 4 UART參考設(shè)計，Xilinx提供VHDL代碼 uart_vhdl This zip file contains the following folders: \vhdl_source -- Source VHDL files: uart.vhd - top level file txmit.vhd - transmit portion of uart rcvr.vhd - - receive portion of uart \vhdl_testfixture -- VHDL Testbench files. This files only include the testbench behavior, they do not instantiate the DUT. This can easily be done in a top-level VHDL file or a schematic. This folder contains the following files: txmit_tb.vhd -- Test bench for txmit.vhd. rcvr_tf.vhd -- Test bench for rcvr.vhd.
標(biāo)簽： UART Xilinx VHDL 參考設(shè)計
上傳時間： 2013-11-02
上傳用戶：18862121743
Abstract: Many modern industrial, medical, and commercial applications require temperature measurements in the extended temperature rangewith accuracies of ±0.3°C or better, performed with reasonable cost and often with low power consumption. This article explains how platinumresistance temperature detectors (PRTDs) can perform measurements over wide temperature ranges of -200°C to +850°C, with absolute accuracyand repeatability better than ±0.3°C, when used with modern processors capable of resolving nonlinear mathematical equation quickly and costeffectively. This article is the second installment of a series on PRTDs. For the first installment, please read application note 4875, "High-Accuracy Temperature Measurements Call for Platinum Resistance Temperature Detectors (PRTDs) and Precision Delta-Sigma ADCs."
上傳時間： 2013-11-06
上傳用戶：WMC_geophy
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