This example provides a description of how to use the USART with hardware flowcontrol and communicate with the Hyperterminal.First, the USART2 sends the TxBuffer to the hyperterminal and still waiting fora string from the hyperterminal that you must enter which must end by '\r'character (keypad ENTER button). Each byte received is retransmitted to theHyperterminal. The string that you have entered is stored in the RxBuffer array. The receivebuffer have a RxBufferSize bytes as maximum.
The USART2 is configured as follow: - BaudRate = 115200 baud - Word Length = 8 Bits - One Stop Bit - No parity - Hardware flow control enabled (RTS and CTS signals) - receive and transmit enabled - USART Clock disabled - USART CPOL: Clock is active low - USART CPHA: Data is captured on the second edge - USART LastBit: The clock pulse of the last data bit is not output to the SCLK pin
This application note covers the design considerations of a system using the performance
features of the LogiCORE™ IP Advanced eXtensible Interface (AXI) Interconnect core. The
design focuses on high system throughput through the AXI Interconnect core with F
MAX
and
area optimizations in certain portions of the design.
The design uses five AXI video direct memory access (VDMA) engines to simultaneously move
10 streams (five transmit video streams and five receive video streams), each in 1920 x 1080p
format, 60 Hz refresh rate, and up to 32 data bits per pixel. Each VDMA is driven from a video
test pattern generator (TPG) with a video timing controller (VTC) block to set up the necessary
video timing signals. Data read by each AXI VDMA is sent to a common on-screen display
(OSD) core capable of multiplexing or overlaying multiple video streams to a single output video
stream. The output of the OSD core drives the DVI video display interface on the board.
Performance monitor blocks are added to capture performance data. All 10 video streams
moved by the AXI VDMA blocks are buffered through a shared DDR3 SDRAM memory and are
controlled by a MicroBlaze™ processor.
The reference system is targeted for the Virtex-6 XC6VLX240TFF1156-1 FPGA on the
Xilinx® ML605 Rev D evaluation board
UART 4 UART參考設計，Xilinx提供VHDL代碼 uart_vhdl
This zip file contains the following folders:
\vhdl_source -- Source VHDL files:
uart.vhd - top level file
txmit.vhd - transmit portion of uart
rcvr.vhd - - receive portion of uart
\vhdl_testfixture -- VHDL Testbench files. This files only include the testbench behavior, they
do not instantiate the DUT. This can easily be done in a top-level VHDL
file or a schematic. This folder contains the following files:
txmit_tb.vhd -- Test bench for txmit.vhd.
rcvr_tf.vhd -- Test bench for rcvr.vhd.
3 pairs of sample codes for basic net apps: . Socket server/client . start the server first . DatagramSocket . start MyDatagramSocketA first . MyDatagramSocketA receive a packet first, and then send a reply MyDatagramSocketA send a packet first, and then receive a reply. . Multicast sender/receiver . start the receiver first
The following Philips LPC2k CAN examples in this directory
were provided by ESAcademy.
LPC2_CANAll_V110:
receives all CAN messages in a receive queue.
LPC2_CANFull_V110:
Uses Full-CAN-like reception filtering.
LPC2_CANBlinky_V130:
Minimal example of MicroCANopen, uses Full-CAN-like
reception filtering and implements both Rx and Tx
Interrupt Service Routines.
The following Philips LPC2k CAN examples in this directory
were provided by ESAcademy.
LPC2_CANAll_V110:
receives all CAN messages in a receive queue.
LPC2_CANFull_V110:
Uses Full-CAN-like reception filtering.
LPC2_CANBlinky_V130:
Minimal example of MicroCANopen, uses Full-CAN-like
reception filtering and implements both Rx and Tx
Interrupt Service Routines.
The following Philips LPC2k CAN examples in this directory
were provided by ESAcademy.
LPC2_CANAll_V110:
receives all CAN messages in a receive queue.
LPC2_CANFull_V110:
Uses Full-CAN-like reception filtering.
LPC2_CANBlinky_V130:
Minimal example of MicroCANopen, uses Full-CAN-like
reception filtering and implements both Rx and Tx
Interrupt Service Routines.
This firmware translates a PS/2 mouse to a USB mouse. The translator
firmware is entirely interrupt driven (with the exception of sending the
data via USB to the host.) An interrupt is generated when the PS/2 start
bit is received, at which time the firmware will begin its receive routine.
In addition to this interrupt, every 168ms a timer overflow interrupts the
main program and implements one state of the mouse state machine. This
state machine handles sending bytes to and translating bytes received from
the PS/2 mouse automatically. All of this is done in the background while
the main program runs in the foreground. The only operation that the main
program implements is sending mouse data to the PC via USB.
This program configures the external memory interface and CAN to receieve data in a FIFO buffer and store the data in XRAM. Meant to receive data from another CAN device.
