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receive

SN65LBC170,SN75LBC170,pdf(TRIP

The SN65LBC170 and SN75LBC170 aremonolithic integrated circuits designed forbidirectional data communication on multipointbus-transmission lines. Potential applicationsinclude serial or parallel data transmission, cabledperipheral buses with twin axial, ribbon, ortwisted-pair cabling. These devices are suitablefor FAST-20 SCSI and can transmit or receivedata pulses as short as 25 ns, with skew lessthan 3 ns.These devices combine three 3-state differentialline drivers and three differential input linereceivers, all of which operate from a single 5-Vpower supply.The driver differential outputs and the receiverdifferential inputs are connected internally to formthree differential input/output (I/O) bus ports thatare designed to offer minimum loading to the buswhenever the driver is disabled or VCC = 0. Theseports feature a wide common-mode voltage rangemaking the device suitable for party-lineapplications over long cable runs.

標簽： 170 LBC SN TRIP

上傳時間： 2013-10-13

上傳用戶：ytulpx
LPC1700以太網MIIM接口應用筆記

The LPC1700 Ethernet block contains a full featured 10 Mbps or 100 Mbps Ethernet MAC (Media Access Controller) designed to provide optimized performance through the use of DMA hardware acceleration. Features include a generous suite of control registers, half or full duplex operation, flow control, control frames, hardware acceleration for transmit retry, receive packet filtering and wake-up on LAN activity. Automatic frame transmission and reception with Scatter-Gather DMA off-loads many operations from the CPU.

標簽： 1700 MIIM LPC 以太網

上傳時間： 2013-11-09

上傳用戶：geshaowei
TJA1042 High-speed CAN transce

The TJA1042 is a high-speed CAN transceiver that provides an interface between aController Area Network (CAN) protocol controller and the physical two-wire CAN bus.The transceiver is designed for high-speed (up to 1 Mbit/s) CAN applications in theautomotive industry, providing the differential transmit and receive capability to (amicrocontroller with) a CAN protocol controller.

標簽： High-speed transce 1042 TJA

上傳時間： 2014-12-28

上傳用戶：氣溫達上千萬的
TJA1051 High-speed CAN transce

The TJA1051 is a high-speed CAN transceiver that provides an interface between aController Area Network (CAN) protocol controller and the physical two-wire CAN bus.The transceiver is designed for high-speed (up to 1 Mbit/s) CAN applications in theautomotive industry, providing differential transmit and receive capability to (amicrocontroller with) a CAN protocol controller.

標簽： High-speed transce 1051 TJA

上傳時間： 2013-10-17

上傳用戶：jisujeke
USB Demonstration for DK3200 w

The μPSD32xx family, from ST, consists of Flash programmable system devices with a 8032 MicrocontrollerCore. Of these, the μPSD3234A and μPSD3254A are notable for having a complete implementationof the USB hardware directly on the chip, complying with the Universal Serial Bus Specification, Revision1.1.This application note describes a demonstration program that has been written for the DK3200 hardwaredemonstration kit (incorporating a μPSD3234A device). It gives the user an idea of how simple it is to workwith the device, using the HID class as a ready-made device driver for the USB connection.IN-APPLICATION-PROGRAMMING (IAP) AND IN-SYSTEM-PROGRAMMING (ISP)Since the μPSD contains two independent Flash memory arrays, the Micro Controller Unit (MCU) can executecode from one memory while erasing and programming the other. Product firmware updates in thefield can be reliably performed over any communication channel (such as CAN, Ethernet, UART, J1850)using this unique architecture. For In-Application-Programming (IAP), all code is updated through theMCU. The main advantage for the user is that the firmware can be updated remotely. The target applicationruns and takes care on its own program code and data memory.IAP is not the only method to program the firmware in μPSD devices. They can also be programmed usingIn-System-Programming (ISP). A IEEE1149.1-compliant JTAG interface is included on the μPSD. Withthis, the entire device can be rapidly programmed while soldered to the circuit board (Main Flash memory,Secondary Boot Flash memory, the PLD, and all configuration areas). This requires no MCU participation.The MCU is completely bypassed. So, the μPSD can be programmed or reprogrammed any time, anywhere, even when completely uncommitted.Both methods take place with the device in its normal hardware environment, soldered to a printed circuitboard. The IAP method cannot be used without previous use of ISP, because IAP utilizes a small amountof resident code to receive the service commands, and to perform the desired operations.

標簽： Demonstration 3200 USB for

上傳時間： 2014-02-27

上傳用戶：zhangzhenyu
24c01a的讀寫程序

#include <at24c01a.h>/*************************************************向24C01A寫入一個字節輸入：E2ROM地址，字節數據******************************************************/void write24c01a(uchar uadd_1,uchar udata_1){sendbyte=0xa0;start();send(sendbyte);if (!ack())continue;send(uadd_1);if (!ack())continue;send(udata_1)if (!ack())continue;stop();}/**********************************發送開始*****************************************/void start(void){a_scl=1;a_sda=1;a_sda=0;a_scl=0;a_scl=1;}/********************************************發送停止*******************************************/void stop(void){a_scl=0;a_sda=0;a_scl=1;a_sda=1;} /*********************************************發送反饋************************************************/bit ack(void){int a_acka_scl=0;a_scl=0;a_scl=0;a_scl=1;a_ack=a_sda;a_scl=0;return(a_ack)}/**************************************發送無反饋********************************************/bit noack(void){int a_ack;a_scl=1;a_scl=1;a_scl=0;}/*******************************************發送****************************************************/void send(uchar undata){uchar i;sendbyte=undatafor(i=8;i>0;i--){a_sda=sendbyte7;a_scl=0;a_scl=1;sendbyte=sendbyte<<1}}/********************************************接受****************************************************/ void receive(void){int i;uchar data;for(i=8;i>0;i--){ a_scl=1;receivebyte7=a_sda;a_scl=0;receivebyte=receivebyte>>1}receivedata=receivebyte;}/********************************************向 24c01a讀一個字節；輸入：EEROM地址；輸出：EEROM數據；********************************************/void read24c01a(uchar counter){receivebyte=0xa1;start();send(receivebyte);if (!ack())continue;send(counter);if (!ack())continue;receive()noack();stop();}

標簽： 24c01a 讀寫程序

上傳時間： 2013-12-23

上傳用戶：wxhwjf
使用CCS進行DSP編程

CCStudio Platinum Edition is available in a number of ways. Existingcustomers who are up-to-date with their subscription service withTexas Instruments will receive their update automatically on a CD inthe mail. New customers who wish to purchase a copy of CCStudioPlatinum Edition can order TMDSCCSALL-1 starting May 23, 2005. A120-day Trial version will be also be available on CDROM startingJuly 11, 2005. Users may order the CDROM of the 120-day free copy

標簽： CCS DSP 編程

上傳時間： 2014-12-28

上傳用戶：gououo
XAPP740利用AXI互聯設計高性能視頻系統

This application note covers the design considerations of a system using the performance features of the LogiCORE™ IP Advanced eXtensible Interface (AXI) Interconnect core. The design focuses on high system throughput through the AXI Interconnect core with F MAX and area optimizations in certain portions of the design. The design uses five AXI video direct memory access (VDMA) engines to simultaneously move 10 streams (five transmit video streams and five receive video streams), each in 1920 x 1080p format, 60 Hz refresh rate, and up to 32 data bits per pixel. Each VDMA is driven from a video test pattern generator (TPG) with a video timing controller (VTC) block to set up the necessary video timing signals. Data read by each AXI VDMA is sent to a common on-screen display (OSD) core capable of multiplexing or overlaying multiple video streams to a single output video stream. The output of the OSD core drives the DVI video display interface on the board. Performance monitor blocks are added to capture performance data. All 10 video streams moved by the AXI VDMA blocks are buffered through a shared DDR3 SDRAM memory and are controlled by a MicroBlaze™ processor. The reference system is targeted for the Virtex-6 XC6VLX240TFF1156-1 FPGA on the Xilinx® ML605 Rev D evaluation board

標簽： XAPP 740 AXI 互聯

上傳時間： 2013-11-14

上傳用戶：fdmpy
UART 4 UART參考設計，Xilinx提供VHDL代碼

UART 4 UART參考設計，Xilinx提供VHDL代碼 uart_vhdl This zip file contains the following folders: \vhdl_source -- Source VHDL files: uart.vhd - top level file txmit.vhd - transmit portion of uart rcvr.vhd - - receive portion of uart \vhdl_testfixture -- VHDL Testbench files. This files only include the testbench behavior, they do not instantiate the DUT. This can easily be done in a top-level VHDL file or a schematic. This folder contains the following files: txmit_tb.vhd -- Test bench for txmit.vhd. rcvr_tf.vhd -- Test bench for rcvr.vhd.

標簽： UART Xilinx VHDL 參考設計

上傳時間： 2013-11-07

上傳用戶：jasson5678
帶有SerDes接口的PLB千兆位級以太網MAC

This application note describes a reference system which illustrates how to build an embeddedPowerPC® system using the Xilinx 1-Gigabit Ethernet Media Access Controller processor core.This system has the PLB_Gemac configured to use Scatter/Gather Direct Memory Access andthe Serializer/Deserializer (SerDes) interface. This application note describes how to set up thespecific clocking structure required for the SerDes interface and the constraints to be added tothe UCF file. This reference system is complete with a standalone software application to testsome of the main features of this core, including access to registers, DMA capabilities, transmitand receive in loopback mode. This reference system is targeted for the ML300 evaluationboard.

標簽： SerDes PLB MAC 接口

上傳時間： 2013-11-01

上傳用戶：truth12