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sequential

sequential Monte Carlo

sequential Monte Carlo

標簽： sequential Monte Carlo

上傳時間： 2014-01-03

上傳用戶：xinyuzhiqiwuwu
program to perform sequential divider in vhdl

program to perform sequential divider in vhdl

標簽： sequential program perform divider

上傳時間： 2013-12-19

上傳用戶：myworkpost
Algorithm GSP in C for patterns sequential

Algorithm GSP in C for patterns sequential

標簽： sequential Algorithm patterns GSP

上傳時間： 2017-07-07

上傳用戶：zhyiroy
This is example for E-Market to use sequential file instead of database.

This is example for E-Market to use sequential file instead of database.

標簽： sequential E-Market database example

上傳時間： 2013-12-27

上傳用戶：lixinxiang
It is n-bit sequential divider in verilog language

It is n-bit sequential divider in verilog language

標簽： sequential language divider verilog

上傳時間： 2017-09-11

上傳用戶：gxf2016
Design Safe Verilog State Machine（Synplicity）

One of the strengths of Synplify is the Finite State Machine compiler. This is a powerfulfeature that not only has the ability to automatically detect state machines in the sourcecode, and implement them with either sequential, gray, or one-hot encoding. But alsoperform a reachability analysis to determine all the states that could possibly bereached, and optimize away all states and transition logic that can not be reached.Thus, producing a highly optimal final implementation of the state machine.

標簽： Synplicity Machine Verilog Design

上傳時間： 2013-10-23

上傳用戶：司令部正軍級
lpc2478完全使用手冊

NXP Semiconductor designed the LPC2400 microcontrollers around a 16-bit/32-bitARM7TDMI-S CPU core with real-time debug interfaces that include both JTAG andembedded Trace. The LPC2400 microcontrollers have 512 kB of on-chip high-speedFlash memory. This Flash memory includes a special 128-bit wide memory interface andaccelerator architecture that enables the CPU to execute sequential instructions fromFlash memory at the maximum 72 MHz system clock rate. This feature is available onlyon the LPC2000 ARM Microcontroller family of products. The LPC2400 can execute both32-bit ARM and 16-bit Thumb instructions. Support for the two Instruction Sets meansEngineers can choose to optimize their application for either performance or code size atthe sub-routine level. When the core executes instructions in Thumb state it can reducecode size by more than 30 % with only a small loss in performance while executinginstructions in ARM state maximizes core performance.

標簽： 2478 lpc 使用手冊

上傳時間： 2013-11-15

上傳用戶：zouxinwang
Design Safe Verilog State Machine（Synplicity）

One of the strengths of Synplify is the Finite State Machine compiler. This is a powerfulfeature that not only has the ability to automatically detect state machines in the sourcecode, and implement them with either sequential, gray, or one-hot encoding. But alsoperform a reachability analysis to determine all the states that could possibly bereached, and optimize away all states and transition logic that can not be reached.Thus, producing a highly optimal final implementation of the state machine.

標簽： Synplicity Machine Verilog Design

上傳時間： 2013-10-20

上傳用戶：蒼山觀海
最新的支持向量機工具箱

最新的支持向量機工具箱，有了它會很方便 1. Find time to write a proper list of things to do! 2. Documentation. 3. Support Vector Regression. 4. Automated model selection. REFERENCES ========== [1] V.N. Vapnik, "The Nature of Statistical Learning Theory", Springer-Verlag, New York, ISBN 0-387-94559-8, 1995. [2] J. C. Platt, "Fast training of support vector machines using sequential minimal optimization", in Advances in Kernel Methods - Support Vector Learning, (Eds) B. Scholkopf, C. Burges, and A. J. Smola, MIT Press, Cambridge, Massachusetts, chapter 12, pp 185-208, 1999. [3] T. Joachims, "Estimating the Generalization Performance of a SVM Efficiently", LS-8 Report 25, Universitat Dortmund, Fachbereich Informatik, 1999.

標簽： 支持向量機工具箱

上傳時間： 2013-12-16

上傳用戶：亞亞娟娟123
This a Bayesian ICA algorithm for the linear instantaneous mixing model with additive Gaussian noise

This a Bayesian ICA algorithm for the linear instantaneous mixing model with additive Gaussian noise [1]. The inference problem is solved by ML-II, i.e. the sources are found by integration over the source posterior and the noise covariance and mixing matrix are found by maximization of the marginal likelihood [1]. The sufficient statistics are estimated by either variational mean field theory with the linear response correction or by adaptive TAP mean field theory [2,3]. The mean field equations are solved by a belief propagation method [4] or sequential iteration. The computational complexity is N M^3, where N is the number of time samples and M the number of sources.

標簽： instantaneous algorithm Bayesian Gaussian

上傳時間： 2013-12-19

上傳用戶：jjj0202

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sequential

sequential Monte Carlo

program to perform sequential divider in vhdl

Algorithm GSP in C for patterns sequential

This is example for E-Market to use sequential file instead of database.

It is n-bit sequential divider in verilog language

Design Safe Verilog State Machine（Synplicity）

lpc2478完全使用手冊

Design Safe Verilog State Machine（Synplicity）

最新的支持向量機工具箱

This a Bayesian ICA algorithm for the linear instantaneous mixing model with additive Gaussian noise