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share是由日本的一位程序員所開發的P2P軟件。他的功能基本上與Winny相同，但是在一定程度上更加容易使用，所以也逐漸被日本本土外的電腦愛好者所使用。該類型的P2P網絡不同于eDonkey和BitTorrent網絡，在share網絡上所有的傳輸都采用了加密措施，所以更能防止被追蹤；同時每個用戶都有一個獨特的ID；以及特有的群集（クラスタ，Cluster）系統、節點（ノード，Node）系統。share的圖標出自日本動畫攻殼機動隊STANDALONECOMPLEX中，一位黑客為隱蔽自己的臉而創造的符號“笑臉男”（笑い男）。

實用的Altium Designer資料自學的朋友可以看看

Altium Designer10軟件+視頻教程+常用元器件原理圖庫+常用PCB庫下載地址： http://pan.baidu.com/share/link?shareid=463765&uk=572810838 歡迎大家加入電子愛好者群 286744774。

標簽： Designer Altium

上傳時間： 2013-10-14

上傳用戶：yt1993410
電源轉換,測量和脈沖電路

This ink marks LTC’s eighth circuit collection publication.1We are continually surprised, to the point of near mystification, by these circuit amalgams seemingly limitlessappeal. Reader requests ascend rapidly upon publication,remaining high for years, even decades. All LTC circuitcollections, despite diverse content, share this popularity,although just why remains an open question. Why isit? Perhaps the form; compact, complete, succinct andinsular. Perhaps the freedom of selection without commitment,akin to window shopping.

標簽： 電源轉換測量脈沖電路

上傳時間： 2014-01-06

上傳用戶：ligi201200
電網現場作業管理系統的信息化設計

為了改變目前電網現場作業管理的變電巡檢、變電檢修試驗、輸電線路巡檢檢修等管理系統各自獨立運行，信息不能共享，功能、效率受限，建設和維護成本高的現狀，提出了采用B/S+C/S構架模式，將各現場作業管理模塊和生產MIS（管理系統）集成為一體的現場作業管理系統的設計方案，做到各子系統和生產MIS軟硬資源共享，做到同一數據唯一入口、一處錄入多處使用。各子系統設備人員等基礎信息來源于生產管理系統，各子系統又是生產管理系統的作業數據、缺陷信息的重要來源。經過研究試用成功和推廣應用，目前該系統已在江西電網220 kV及以上變電站全面應用。 Abstract: In order to improve the status that the substation field inspection system， substation equipments maintenance and testing system， power-line inspection and maintenance system are running independent with each other. They can?蒺t share the resource information which accordingly constrains their functions and efficiency， and their construction and maintenance costs are high. This paper introduces a field standardized work management system based on B/S+C/S mode， integrating all field work management systems based on MIS and share the equipments and employee?蒺s data of MIS，the field work data of the sub systems are the source information of MIS， by which the same single data resouce with one-time input can be utilized in multiple places. After the research and testing， this system is triumphantly using in all 220kV and above substations in Jiangxi grid.

標簽： 電網信息化管理系統

上傳時間： 2013-11-15

上傳用戶：han_zh
FREERTOS的官方移植文檔

FeaturesThe following standard features are provided.• Choice of RTOS scheduling policy1. Pre-emptive:Always runs the highest available task. Tasks of identical priorityshare CPU time (fully pre-emptive with round robin time slicing).2. Cooperative:Context switches only occur if a task blocks, or explicitly callstaskYIELD().• Co-routines (light weight tasks that utilise very little RAM).• Message queues• Semaphores [via macros]• Trace visualisation ability (requires more RAM)• Majority of source code common to all supported development tools• Wide range of ports and examples

標簽： FREERTOS 移植文檔

上傳時間： 2013-10-13

上傳用戶：13162218709
基于Xilinx FPGA的雙輸出DC/DC轉換器解決方案

Xilinx FPGAs require at least two power supplies: VCCINTfor core circuitry and VCCO for I/O interface. For the latestXilinx FPGAs, including Virtex-II Pro, Virtex-II and Spartan-3, a third auxiliary supply, VCCAUX may be needed. Inmost cases, VCCAUX can share a power supply with VCCO.The core voltages, VCCINT, for most Xilinx FPGAs, rangefrom 1.2V to 2.5V. Some mature products have 3V, 3.3Vor 5V core voltages. Table 1 shows the core voltagerequirement for most of the FPGA device families. TypicalI/O voltages (VCCO) vary from 1.2V to 3.3V. The auxiliaryvoltage VCCAUX is 2.5V for Virtex-II Pro and Spartan-3, andis 3.3V for Virtex-II.

標簽： Xilinx FPGA DC 輸出

上傳時間： 2013-10-22

上傳用戶：liu999666
展訊低成本1GHz智能手機方案中文PDF

目錄一、Smart Phone Market share 1.1、中國智能手機銷售量與變化狀況 1.2、智能手機操作系統份額走勢 1.3、智能手機銷售價格走勢二、展訊智能手機方案三、TI 無線充電方案四、Freescale G+M二合一 Sensor 五、NXP NFC 六、TI 五合一無線芯片展訊智能手機方案框圖

標簽： 1GHz 展訊智能手機

上傳時間： 2014-12-30

上傳用戶：blacklee
實用的Altium Designer資料自學的朋友可以看看

Altium Designer10軟件+視頻教程+常用元器件原理圖庫+常用PCB庫下載地址： http://pan.baidu.com/share/link?shareid=463765&uk=572810838 歡迎大家加入電子愛好者群 286744774。

標簽： Designer Altium

上傳時間： 2013-11-21

上傳用戶：66666
怎樣使用Nios II處理器來構建多處理器系統

怎樣使用Nios II處理器來構建多處理器系統 Chapter 1. Creating Multiprocessor Nios II Systems Introduction to Nios II Multiprocessor Systems . . . . . . . . . . . . . . 1–1 Benefits of Hierarchical Multiprocessor Systems . . . . . . . . . . . . . . . 1–2 Nios II Multiprocessor Systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–2 Multiprocessor Tutorial Prerequisites . . . . . . . . . . . . . . . . . . . . . . . 1–3 Hardware Designs for Peripheral Sharing . . . . . . . . . . . .. . . . . . . . 1–3 Autonomous Multiprocessors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–3 Multiprocessors that share Peripherals . . . . . . . . . . . . . . . . . . . . . . 1–4 Sharing Peripherals in a Multiprocessor System . . . . . . . . . . . . . . . . . 1–4 Sharing Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–6 The Hardware Mutex Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–7 Sharing Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . 1–8 Overlapping Address Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–8 Software Design Considerations for Multiple Processors . . .. . . . . 1–9 Program Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–9 Boot Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1–13 Debugging Nios II Multiprocessor Designs . . . . . . . . . . . . . . . . 1–15 Design Example: The Dining Philosophers’ Problem . . . . .. . . 1–15 Hardware and Software Requirements . . . . . . . . . . . . . . . .. . . 1–16 Installation Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–17 Creating the Hardware System . . . . . . . . . . . . . . .. . . . . . 1–17 Getting Started with the multiprocessor_tutorial_start Design Example 1–17 Viewing a Philosopher System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–18 Philosopher System Pipeline Bridges . . . . . . . . . . . . . . . . . . . . . 1–19 Adding Philosopher Subsystems . . . . . . . . . . . . . . . . . . . . . . . . . . 1–21 Connecting the Philosopher Subsystems . . . . . . . . . . . . .. . . . . 1–22 Viewing the Complete System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–27 Generating and Compiling the System . . . . . . . . . . . . . . . . . .. 1–28

標簽： Nios 處理器多處理器

上傳時間： 2013-11-21

上傳用戶：lo25643
基于Xilinx FPGA的雙輸出DC/DC轉換器解決方案

Xilinx FPGAs require at least two power supplies: VCCINTfor core circuitry and VCCO for I/O interface. For the latestXilinx FPGAs, including Virtex-II Pro, Virtex-II and Spartan-3, a third auxiliary supply, VCCAUX may be needed. Inmost cases, VCCAUX can share a power supply with VCCO.The core voltages, VCCINT, for most Xilinx FPGAs, rangefrom 1.2V to 2.5V. Some mature products have 3V, 3.3Vor 5V core voltages. Table 1 shows the core voltagerequirement for most of the FPGA device families. TypicalI/O voltages (VCCO) vary from 1.2V to 3.3V. The auxiliaryvoltage VCCAUX is 2.5V for Virtex-II Pro and Spartan-3, andis 3.3V for Virtex-II.

標簽： Xilinx FPGA DC 輸出

上傳時間： 2013-10-22

上傳用戶：aeiouetla
XAPP713 -Virtex-4 RocketIO誤碼率測試器

The data plane of the reference design consists of a configurable multi-channel XBERT modulethat generates and checks high-speed serial data transmitted and received by the MGTs. Eachchannel in the XBERT module consists of two MGTs (MGTA and MGTB), which physicallyoccupy one MGT tile in the Virtex-4 FPGA. Each MGT has its own pattern checker, but bothMGTs in a channel share the same pattern generator. Each channel can load a differentpattern. The MGT serial rate depends on the reference clock frequency and the internal PMAdivider settings. The reference design can be scaled anywhere from one channel (two MGTs)to twelve channels (twenty-four MGTs).

標簽： RocketIO Virtex XAPP 713

上傳時間： 2013-12-25

上傳用戶：jkhjkh1982

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