High volume USB 2.0 devices will be designed using ASIC technology with embedded USB 2.0 support.
For full-speed USB devices the operating frequency was low enough to allow data recovery to be handled
in a vendors VHDL code, with the ASIC vendor providing only a simple level translator to meet the USB
signaling requirements. Today s gate arrays operate comfortably between 30 and 60 MHz. With USB 2.0
signaling running at hundreds of MHz, the existing design methodology must change.
標(biāo)簽：
technology
2.0
USB
designed
上傳時(shí)間：
2017-07-05
上傳用戶：zhoujunzhen
