This manual describes SAMSUNG s S3C2410A 16/32-bit RISC microprocessor. This product is designed to provide
hand-held devices and general applications with cost-effective, low-power, and high-performance micro-controller
solution in small die size. To reduce total system cost, the S3C2410A includes the following components separate
16KB Instruction and 16KB Data Cache, MMU to handle virtual memory management, LCD Controller (STN & TFT),
NAND Flash Boot Loader, System Manager (chip select logic and SDRAM Controller), 3-ch UART, 4-ch DMA, 4-ch
Timers with PWM, I/O Ports, RTC, 8-ch 10-bit ADC and Touch Screen Interface, IIC-BUS Interface, IIS-BUS
Interface, USB Host, USB Device, SD Host & Multi-Media Card Interface, 2-ch SPI and PLL for clock generation.
This manual describes SAMSUNG s S3C2410X 16/32-bit RISC microprocessor. This product is designed to
provide hand-held devices and general applications with cost-effective, low-power, and high-performance microcontroller
solution in small die size. To reduce total system cost, the S3C2410X includes the following
components separate 16KB Instruction and 16KB Data Cache, MMU to handle virtual memory management,
LCD Controller (STN & TFT), NAND Flash Boot Loader, System Manager (chip select logic and SDRAM
Controller), 3-ch UART, 4-ch DMA, 4-ch Timers with PWM, I/O Ports, RTC, 8-ch 10-bit ADC and Touch Screen
Interface, IIC-BUS Interface, IIS-BUS Interface, USB Host, USB Device, SD Host & Multi-Media Card Interface,
2-ch SPI and PLL for clock generation.
The surge of mobile data traffic forces network
operators to cope with capacity shortage. The deployment of
small cells in 5G networks is meant to reduce latency, backhaul
traffic and increase radio access capacity. In this context, mobile
edge computing technology will be used to manage dedicated
cache space in the radio access network. Thus, mobile network
operators will be able to provision OTT content providers with
new caching services to enhance the quality of experience of their
customers on the move.
