<sup id="gg8gm"></sup>
元器件樣本專輯 116冊(cè) 3.03GD-sub-jy.pdf
標(biāo)簽：
上傳時(shí)間： 2014-05-05
上傳用戶：時(shí)代將軍
We introduce a sub-cell WENO reconstruction method to evaluate spatial derivatives in the high-order ADER scheme. The basic idea in our reconstruction is to use only r stencils to reconstruct the point-wise values of solutions and spatial derivatives for the 2r-1 th order ADER scheme in one dimension, while in two dimensions, the dimension-by-dimension sub-cell reconstruction approach for spatial derivatives is employed. Compared with the original ADER scheme of Toro and Titarev (2002) [2] that uses the direct derivatives of reconstructed polynomials for solutions to evaluate spatial derivatives, our method not only reduces greatly the computational costs of the ADER scheme on a given mesh, but also avoids possible numerical oscillations near discontinuities, as demonstrated by a number of one- and two-dimensional numerical tests. All these tests show that the 5th-order ADER scheme based on our sub-cell reconstruction method achieves the desired accuracy, and is essentially non-oscillatory and computationally cheaper for problems with discontinuities.
標(biāo)簽： 高精度格式
上傳時(shí)間： 2016-01-13
上傳用戶：ccsdcczd
采用現(xiàn)場(chǎng)可編程門陣列(FPGA)可以快速實(shí)現(xiàn)數(shù)字電路，但是用于生成FPGA編程的比特流文件的CAD工具在編制大規(guī)模電路時(shí)常常需要數(shù)小時(shí)的時(shí)間，以至于許多設(shè)計(jì)者甚至通過(guò)在給定FPGA上采用更多的資源，或者以犧牲電路速度為代價(jià)來(lái)提高編制速度。電路編制過(guò)程中大部分時(shí)間花費(fèi)在布線階段，因此有效的布線算法能極大地減少布線時(shí)間。 許多布線算法已經(jīng)被開發(fā)并獲得應(yīng)用，其中布爾可滿足性(SAT)布線算法及幾何查找布線算法是當(dāng)前最為流行的兩種。然而它們各有缺點(diǎn)：基于SAT的布線算法在可擴(kuò)展性上有很大缺陷；幾何查找布線算法雖然具有廣泛的拆線重布線能力，但當(dāng)實(shí)際問(wèn)題具有嚴(yán)格的布線約束條件時(shí)，它在布線方案的收斂方面存在很大困難。基于此，本文致力于探索一種能有效解決以上問(wèn)題的新型算法，具體研究工作和結(jié)果可歸納如下。 1、在全面調(diào)查FPGA結(jié)構(gòu)的最新研究動(dòng)態(tài)的基礎(chǔ)上，確定了一種FPGA布線結(jié)構(gòu)模型，即一個(gè)基于SRAM的對(duì)稱陣列(島狀)FPGA結(jié)構(gòu)作為研究對(duì)象，該模型僅需3個(gè)適合的參數(shù)即能表示布線結(jié)構(gòu)。為使所有布線算法可在相同平臺(tái)上運(yùn)行，選擇了美國(guó)北卡羅來(lái)納州微電子中心的20個(gè)大規(guī)模電路作為基準(zhǔn)，并在布線前采用VPR399對(duì)每個(gè)電路都生成30個(gè)布局，從而使所有的布線算法都能夠直接在這些預(yù)制電路上運(yùn)行。 2、詳細(xì)研究了四種幾何查找布線算法，即一種基本迷宮布線算法Lee，一種基于協(xié)商的性能驅(qū)動(dòng)的布線算法PathFinder，一種快速的時(shí)延驅(qū)動(dòng)的布線算法VPR430和一種協(xié)商A
上傳時(shí)間： 2013-05-18
上傳用戶：ukuk
This document was developed under the Standard Hardware and Reliability Program (SHARP) TechnologyIndependent Representation of Electronic Products (TIREP) project. It is intended for use by VHSIC HardwareDescription Language (VHDL) design engineers and is offered as guidance for the development of VHDL modelswhich are compliant with the VHDL Data Item Description (DID DI-EGDS-80811) and which can be providedto manufacturing engineering personnel for the development of production data and the subsequent productionof hardware. Most VHDL modeling performed to date has been concentrated at either the component level orat the conceptual system level. The assembly and sub-assembly levels have been largely disregarded. Under theSHARP TIREP project, an attempt has been made to help close this gap. The TIREP models are based upon lowcomplexity Standard Electronic Modules (SEM) of the format A configuration. Although these modules are quitesimple, it is felt that the lessons learned offer guidance which can readily be applied to a wide range of assemblytypes and complexities.
標(biāo)簽： Modelling Guide Navy VHDL
上傳時(shí)間： 2014-12-23
上傳用戶：xinhaoshan2016
The MAX2691 low-noise amplifier (LNA) is designed forGPS L2 applications. Designed in Maxim’s advancedSiGe process, the device achieves high gain andlow noise figure while maximizing the input-referred 1dBcompression point and the 3rd-order intercept point. TheMAX2691 provides a high gain of 17.5dB and sub 1dBnoise figure.
標(biāo)簽： Amplifier Low-Noise 2691 Band
上傳時(shí)間： 2014-12-04
上傳用戶：zaocan888
為了改變目前電網(wǎng)現(xiàn)場(chǎng)作業(yè)管理的變電巡檢、變電檢修試驗(yàn)、輸電線路巡檢檢修等管理系統(tǒng)各自獨(dú)立運(yùn)行，信息不能共享，功能、效率受限，建設(shè)和維護(hù)成本高的現(xiàn)狀，提出了采用B/S+C/S構(gòu)架模式，將各現(xiàn)場(chǎng)作業(yè)管理模塊和生產(chǎn)MIS（管理系統(tǒng)）集成為一體的現(xiàn)場(chǎng)作業(yè)管理系統(tǒng)的設(shè)計(jì)方案，做到各子系統(tǒng)和生產(chǎn)MIS軟硬資源共享，做到同一數(shù)據(jù)唯一入口、一處錄入多處使用。各子系統(tǒng)設(shè)備人員等基礎(chǔ)信息來(lái)源于生產(chǎn)管理系統(tǒng)，各子系統(tǒng)又是生產(chǎn)管理系統(tǒng)的作業(yè)數(shù)據(jù)、缺陷信息的重要來(lái)源。經(jīng)過(guò)研究試用成功和推廣應(yīng)用，目前該系統(tǒng)已在江西電網(wǎng)220 kV及以上變電站全面應(yīng)用。 Abstract: In order to improve the status that the substation field inspection system， substation equipments maintenance and testing system， power-line inspection and maintenance system are running independent with each other. They can?蒺t share the resource information which accordingly constrains their functions and efficiency， and their construction and maintenance costs are high. This paper introduces a field standardized work management system based on B/S+C/S mode， integrating all field work management systems based on MIS and share the equipments and employee?蒺s data of MIS，the field work data of the sub systems are the source information of MIS， by which the same single data resouce with one-time input can be utilized in multiple places. After the research and testing， this system is triumphantly using in all 220kV and above substations in Jiangxi grid.
標(biāo)簽： 電網(wǎng) 信息化 管理系統(tǒng)
上傳時(shí)間： 2013-11-15
上傳用戶：han_zh
顯卡所處理的信息最終都要輸出到顯示器上，顯卡的輸出接口就是電腦不顯示器之間的橋梁，它負(fù)責(zé)向顯示器輸出相應(yīng)的圖像信號(hào)。CRT顯示器因?yàn)樵O(shè)計(jì)制造上的原因，只能接受模擬信號(hào)輸入，這就需要顯卡能輸入模擬信號(hào)。VGA接口就是顯卡上輸出模擬信號(hào)的接口，VGA（Video Graphics Array）接口，也叫D-Sub接口。雖然液晶顯示器可以直接接收數(shù)字信號(hào)，但為了兼容性，大多數(shù)液晶顯示器也配備了VGA接口。 VGA是IBM在1987年隨PS／2機(jī)一起推出的一種視頻傳輸標(biāo)準(zhǔn)，具有分辨率高、顯示速率快、顏色豐富等優(yōu)點(diǎn)，在彩色顯示器領(lǐng)域得到了廣泛的應(yīng)用。目前VGA技術(shù)的應(yīng)用還主要基亍VGA顯示卡的計(jì)算機(jī)、筆記本等設(shè)備。 根據(jù)分辨率丌同，VGA分為VGA（640x480）、SVGA（800x600）、XGA（1024x768）、SXGA（1280x1024）等。
標(biāo)簽： VGA 驅(qū)動(dòng) 實(shí)現(xiàn)方法
上傳時(shí)間： 2013-10-22
上傳用戶：macarco
NXP Semiconductor designed the LPC2400 microcontrollers around a 16-bit/32-bitARM7TDMI-S CPU core with real-time debug interfaces that include both JTAG andembedded Trace. The LPC2400 microcontrollers have 512 kB of on-chip high-speedFlash memory. This Flash memory includes a special 128-bit wide memory interface andaccelerator architecture that enables the CPU to execute sequential instructions fromFlash memory at the maximum 72 MHz system clock rate. This feature is available onlyon the LPC2000 ARM Microcontroller family of products. The LPC2400 can execute both32-bit ARM and 16-bit Thumb instructions. Support for the two Instruction Sets meansEngineers can choose to optimize their application for either performance or code size atthe sub-routine level. When the core executes instructions in Thumb state it can reducecode size by more than 30 % with only a small loss in performance while executinginstructions in ARM state maximizes core performance.
上傳時(shí)間： 2013-11-15
上傳用戶：zouxinwang
由于近些年來(lái)智能電網(wǎng)的大力發(fā)展需求出現(xiàn)了各種自動(dòng)抄表系統(tǒng)的應(yīng)用方案，但各有不足之處未能真正在我國(guó)廣泛采用。為了實(shí)現(xiàn)智能電網(wǎng)自動(dòng)抄表系統(tǒng)的真正應(yīng)用，設(shè)計(jì)了一種易于實(shí)現(xiàn)的、網(wǎng)絡(luò)開銷小并低功耗的無(wú)線網(wǎng)絡(luò)，它采用ARM和MCU作為自動(dòng)抄表系統(tǒng)的無(wú)線集中器硬件平臺(tái)，并搭配Sub-GHz的射頻收發(fā)模塊，集中器與節(jié)點(diǎn)設(shè)備之間采用自定義協(xié)議的自動(dòng)組網(wǎng)形式， 可實(shí)現(xiàn)50個(gè)節(jié)點(diǎn)自動(dòng)靈活組網(wǎng)，而且網(wǎng)絡(luò)開銷小只占用4 k存儲(chǔ)空間。整個(gè)系統(tǒng)具有實(shí)用性和應(yīng)用性強(qiáng)的特點(diǎn)。
標(biāo)簽： 自動(dòng)抄表 低功耗 無(wú)線 網(wǎng)絡(luò)設(shè)計(jì)
上傳時(shí)間： 2013-10-17
上傳用戶：fqscfqj
糧食安全一直是人民生活重點(diǎn)關(guān)注的話題，在糧食的儲(chǔ)備過(guò)程中，對(duì)糧食的溫濕度以及蟲害等的監(jiān)測(cè)是保持糧食安全的重要措施。文中設(shè)計(jì)了一個(gè)通過(guò)采用Sub-G Hz頻段和CDMA技術(shù)進(jìn)行融合的糧情監(jiān)測(cè)系統(tǒng)，系統(tǒng)將物聯(lián)網(wǎng)與互聯(lián)網(wǎng)聯(lián)合起來(lái)，將采集到的數(shù)據(jù)通過(guò)CDMA網(wǎng)絡(luò)傳輸?shù)竭h(yuǎn)端的PC上，然后通過(guò)上位機(jī)對(duì)數(shù)據(jù)分析后進(jìn)行相應(yīng)的處理，從而實(shí)現(xiàn)對(duì)糧食遠(yuǎn)程的監(jiān)測(cè)與控制。該系統(tǒng)具有傳輸距離遠(yuǎn)、成本低和低功耗等特點(diǎn)，具有良好的應(yīng)用前景。
標(biāo)簽： 無(wú)線傳感器網(wǎng)絡(luò) 監(jiān)測(cè)系統(tǒng)
上傳時(shí)間： 2013-12-24
上傳用戶：taiyang250072
蟲蟲下載站版權(quán)所有 京ICP備2021023401號(hào)-1
