本文主要介紹如何在Wado設計套件中進行時序約束，原文出自 xilinx中文社區。1 Timing Constraints in Vivado-UCF to xdcVivado軟件相比于sE的一大轉變就是約束文件，5E軟件支持的是UcF（User Constraints file，而 Vivado軟件轉換到了XDc（Xilinx Design Constraints）。XDC主要基于SDc（synopsys Design Constraints）標準，另外集成了Xinx的一些約束標準可以說這一轉變是xinx向業界標準的靠攏。Altera從 TimeQuest開始就一直使用SDc標準，這一改變，相信對于很多工程師來說是好事，兩個平臺之間的轉換會更加容易些。首先看一下業界標準SDc的原文介紹：synopsys widely-used design constraints format, known as sDc, describes the design intent"and surrounding constraints for synthesis, clocking, timing, power, test and environmental and operating conditions. sDc has been in use and evolving for more than 20 years, making it the most popular and proven format for describing design constraints. Essentially all synthesized designs use SDc and numerous EDa companies have translators that can read and process sDc
標簽：
vivado
上傳時間：
2022-03-26
上傳用戶：
