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synthesizable

synthesizable Verilo---syntax and semantics一本很好的關(guān)于verilog可綜合設(shè)計(jì)的參考書

synthesizable Verilo---syntax and semantics一本很好的關(guān)于verilog可綜合設(shè)計(jì)的參考書

標(biāo)簽： synthesizable semantics verilog Verilo

上傳時(shí)間： 2015-02-16

上傳用戶：葉山豪
synthesizable model of Atmel ATmega103 microcontroller. (VHDL IP)

synthesizable model of Atmel ATmega103 microcontroller. (VHDL IP)

標(biāo)簽： microcontroller synthesizable ATmega Atmel

上傳時(shí)間： 2013-11-30

上傳用戶：z754970244
Lab 2 – synthesizable MATLAB This lab exercise will explore the effects that different MATLAB codin

Lab 2 – synthesizable MATLAB This lab exercise will explore the effects that different MATLAB coding styles have on hardware. The lab has two parts, each of which begins with a short introduction. This lab exercise is based on the simple MATLAB FIR filter model shown below:

標(biāo)簽： MATLAB synthesizable different exercise

上傳時(shí)間： 2015-09-28

上傳用戶：sammi
PacoBlaze is a from-scratch synthesizable & behavioral Verilog clone of Ken Chapman s popular PicoB

PacoBlaze is a from-scratch synthesizable & behavioral Verilog clone of Ken Chapman s popular PicoBlaze embedded microcontroller. by Pablo Bleyer Kocik

標(biāo)簽： synthesizable from-scratch behavioral PacoBlaze

上傳時(shí)間： 2013-12-09

上傳用戶：hphh
synthesizable FIFO Model This example describes a synthesizable implementation of a FIFO. The FIFO

synthesizable FIFO Model This example describes a synthesizable implementation of a FIFO. The FIFO depth and FIFO width in bits can be modified by simply changing the value of two parameters, `FWIDTH and `FDEPTH. For this example, the FIFO depth is 4 and the FIFO width is 32 bits.

標(biāo)簽： FIFO implementation synthesizable synthesizable

上傳時(shí)間： 2016-02-12

上傳用戶：源弋弋
Verilog module containing a synthesizable CRC function // * polynomial: (0 1 8) // * data width: 8

Verilog module containing a synthesizable CRC function // * polynomial: (0 1 8) // * data width: 8

標(biāo)簽： synthesizable containing polynomial function

上傳時(shí)間： 2016-09-26

上傳用戶：lacsx
實(shí)用的I2C程序。This example describes a synthesizable implementation of a I2C.

實(shí)用的I2C程序。This example describes a synthesizable implementation of a I2C.

標(biāo)簽： implementation synthesizable describes example

上傳時(shí)間： 2014-01-02

上傳用戶：zhouli
與外部設(shè)備進(jìn)行成功連接的完整I2C程序。This example describes a synthesizable implementation of a I2C.

與外部設(shè)備進(jìn)行成功連接的完整I2C程序。This example describes a synthesizable implementation of a I2C.

標(biāo)簽： implementation synthesizable describes example

上傳時(shí)間： 2017-01-24

上傳用戶：jichenxi0730
The Synthetic PIC Verion 1.1 This a VHDL synthesizable model of a simple PIC 16C5x microcontro

The Synthetic PIC Verion 1.1 This a VHDL synthesizable model of a simple PIC 16C5x microcontroller. It is not, and is not intended as, a high fidelity circuit simulation. This package includes the following files. Note that the license agreement is stated in the main VHDL file, PICCPU.VHD and common questions are answered in the file SYNTHPIC.TXT Files: README.TXT This file.. SYNTHPIC.TXT Questions and Answers PICCPU.VHD Main processor VHDL file PICALU.VHD ALU for the PICCPU PICREGS.VHD Data memory PICROM.VHD Program memory (created by HEX2VHDL utility) PICTEST.VHD Simple test bench I used to do testing (optional) PICTEST.CMD My Viewlogic ViewSim command file (again, optional) TEST1.ASM First program I assembled and ran on it. TEST2.ASM Another test program.. TEST3.ASM Yet another.. TEST4.ASM Yet another.. TEST5.ASM Yet another.. TEST6.ASM Yet another.. HEX2VHDL.CPP Utility for converting

標(biāo)簽： synthesizable microcontro Synthetic PIC

上傳時(shí)間： 2013-12-22

上傳用戶：妄想演繹師
synthesizable code for shift register of user defined size

synthesizable code for shift register of user defined size

標(biāo)簽： synthesizable register defined shift

上傳時(shí)間： 2017-05-30

上傳用戶：gengxiaochao

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synthesizable

synthesizable Verilo---syntax and semantics一本很好的關(guān)于verilog可綜合設(shè)計(jì)的參考書

synthesizable model of Atmel ATmega103 microcontroller. (VHDL IP)

Lab 2 – synthesizable MATLAB This lab exercise will explore the effects that different MATLAB codin

PacoBlaze is a from-scratch synthesizable & behavioral Verilog clone of Ken Chapman s popular PicoB

synthesizable FIFO Model This example describes a synthesizable implementation of a FIFO. The FIFO

Verilog module containing a synthesizable CRC function // * polynomial: (0 1 8) // * data width: 8

實(shí)用的I2C程序。This example describes a synthesizable implementation of a I2C.

與外部設(shè)備進(jìn)行成功連接的完整I2C程序。This example describes a synthesizable implementation of a I2C.

The Synthetic PIC Verion 1.1 This a VHDL synthesizable model of a simple PIC 16C5x microcontro

synthesizable code for shift register of user defined size