System Generator 9.10
System Generator 8.1。用戶將很快發(fā)現(xiàn)新版本帶來的全新感覺。新版本中大大增強(qiáng)了Block Dialog Boxes的功能，許多模塊的參數(shù)選擇功能也得到了加強(qiáng)。...
system技術(shù)資料
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03 calgary PhD Improving the Inertial Navigation System (INS) Error Model for INS and INSDGPS Applic
資料->【E】光盤論文->【E1】斯坦福博士論文->03 calgary PhD Improving the Inertial Navigation System (INS) Error Model ...
This brief introduce a kind of the framework construction to materialize the system. And an example
This brief introduce a kind of the framework construction to materialize the system. And an example ...
Building a RISC System in an FPGA
Building a RISC System in an FPGA...
EDA系統(tǒng)軟件ispDesignExpert System 環(huán)境下進(jìn)行數(shù)字系統(tǒng)設(shè)計(jì)
本設(shè)計(jì)的基本要求是以復(fù)雜可編程邏輯器件CPLD為基礎(chǔ)，通過在EDA系統(tǒng)軟件ispDesignExpert System 環(huán)境下進(jìn)行數(shù)字系統(tǒng)設(shè)計(jì)，熟練掌握該環(huán)境下的功能仿真，時(shí)間仿真，管腳鎖定和芯片下載...
System will automatically delete the directory
System will automatically delete the directory...
VHDL,Verilog,System verilog比較
本文簡單討論并總結(jié)了VHDL、Verilog，System verilog 這三中語言的各自特點(diǎn)和區(qū)別As the number of enhancements to vario...
High-Speed Digital System Design
Introduce High-Speed Digital System Design....
基于System Generator的數(shù)字下變頻設(shè)計(jì)
Xilinx公司推出的DSP設(shè)計(jì)開發(fā)工具System Generator是在Matlab環(huán)境中進(jìn)行建模，是DSP高層系統(tǒng)設(shè)計(jì)與Xilinx FPGA之間實(shí)現(xiàn)的“橋梁”。在分析了...
Control System of Stepp ingMot
提出了一個(gè)由AT89C52單片機(jī)控制步進(jìn)電機(jī)的實(shí)例。可以通過鍵盤輸入相關(guān)數(shù)據(jù), 并根據(jù)需要, 實(shí)時(shí)對步進(jìn)電機(jī)工作方式進(jìn)行設(shè)置, 具有實(shí)時(shí)性和交互性的特點(diǎn)。該系統(tǒng)可應(yīng)用于步進(jìn)電機(jī)控制的大多數(shù)場合。實(shí)踐表...