A Huffman implementation reference design in both VHDL and Verilog is provided by the Xilinx
標(biāo)簽： implementation reference provided Huffman
上傳時(shí)間： 2015-07-07
上傳用戶：cooran
通用存儲(chǔ)器VHDL代碼庫,The Free IP Project VHDL Free-FIFO, Quartus standard library.
標(biāo)簽： VHDL Free-FIFO standard Project
上傳時(shí)間： 2013-12-12
上傳用戶：天涯
the samples of VHDL very usef
標(biāo)簽： samples VHDL very usef
上傳時(shí)間： 2015-07-25
上傳用戶：moerwang
Language writes with VHDL demonstrates the design on the monitor the source program用VHDL 語言寫的在顯示器上顯示圖案的程序
標(biāo)簽： the VHDL demonstrates Language
上傳時(shí)間： 2015-10-14
上傳用戶：ardager
8051的內(nèi)核(vhdl) This is version 1.1. of the MC8051 IP core. 在FPGA上運(yùn)行.供有精力的人研究.
標(biāo)簽： 8051 version vhdl This
上傳時(shí)間： 2013-12-16
上傳用戶：gdgzhym
VHDL實(shí)現(xiàn)SPI功能源代碼 -- The SPI bus is a 3 wire bus that in effect links a serial shift -- register between the "master" and the "slave". Typically both the -- master and slave have an 8 bit shift register so the combined -- register is 16 bits. When an SPI transfer takes place, the master and -- slave shift their shift registers 8 bits and thus exchange their 8 -- bit register values.
標(biāo)簽： SPI bus register effect
上傳時(shí)間： 2013-12-23
上傳用戶：lx9076
Triscend supports the use of the Model Technology ModelSim logic simulator for VHDL simulation of designs implemented in the Configurable System Logic (CSL) portion of a Triscend device.
標(biāo)簽： Technology simulation simulator the
上傳時(shí)間： 2013-12-26
上傳用戶：zl5712176
This a vhdl programme for realise an electron watch by max-plus II. The function includes time showing and time setting. It may be extended to other functions like alarming clock and so forth.
標(biāo)簽： programme electron max-plus function
上傳時(shí)間： 2013-12-26
上傳用戶：dbs012280
This program shows the distributions of the co-channel interference in forward and reverse link in the cellular mobile system with cluster size N, when the mobile subscriber (MS) is at random positions of a cell.
標(biāo)簽： distributions interference co-channel the
上傳時(shí)間： 2014-01-15
上傳用戶：z754970244
CF VHDL The CF+ design was designed using the timing diagrams of the Compact Flash specification rev. 1.4, Analog Devices ADSP-218xN DSP Microcomputer specification, and the Intel StrataFlash Memory 28F320J3 specification.
標(biāo)簽： specification the designed diagrams
上傳時(shí)間： 2013-12-27
上傳用戶：yyyyyyyyyy
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