This m file simulates a differential phase shift keyed (DPSK) ultra wide bandwidth(UWB) system using a fifth derivative waveform equation of a Gaussian pulse.
標(biāo)簽： differential bandwidth simulates system
上傳時(shí)間： 2014-01-03
上傳用戶：784533221
The ADC0803 family is a series of three CMOS 8-bit successive approximation A/D converters using a resistive ladder and capacitive array together with an auto-zero comparator. These converters are designed to operate with microprocessor-controlled buses using a minimum of external circuitry. The 3-State output data lines can be connected directly to the data bus.
標(biāo)簽： approximation converters successive family
上傳時(shí)間： 2016-11-20
上傳用戶：libenshu01
Range imaging offers an inexpensive and accurate means for digitizing the shape of three-dimensional objects. Because most objects self occlude, no single range image suffices to describe the entire object. We present a method for combining a collection of range images into a single polygonal mesh that completely describes an object to the extent that it is visible from the outside.
標(biāo)簽： three-dimensiona inexpensive digitizing accurate
上傳時(shí)間： 2016-11-29
上傳用戶：yxgi5
script for generting transmit waveforms in a minimum shift keying, a form of continuous phase frequency shift keying
標(biāo)簽： continuous generting waveforms transmit
上傳時(shí)間： 2016-11-30
上傳用戶：ANRAN
This program is about Compilers.A source routine that need to be compiled need process three sections.It is about the third section.
標(biāo)簽： need Compilers compiled program
上傳時(shí)間： 2016-12-01
上傳用戶：zm7516678
ADPLL of high level phase locked loop
標(biāo)簽： locked ADPLL level phase
上傳時(shí)間： 2016-12-04
上傳用戶：wpwpwlxwlx
A high-speed variable phase accumulator for an ADPLL architecture
標(biāo)簽： architecture accumulator high-speed variable
上傳時(shí)間： 2013-11-26
上傳用戶：wpt
A Top-Down Verilog-A Design on the digital phase-lockedmloop
標(biāo)簽： phase-lockedmloop Verilog-A Top-Down digital
上傳時(shí)間： 2013-12-02
上傳用戶：silenthink
A Stochastic Time-to-Digital Converter for Digital Phase-Locked Loops
標(biāo)簽： Time-to-Digital Phase-Locked Stochastic Converter
上傳時(shí)間： 2014-01-16
上傳用戶：ANRAN
Ethernet Services Attributes Phase
標(biāo)簽： Attributes Ethernet Services Phase
上傳時(shí)間： 2013-12-13
上傳用戶：xhz1993
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