Abstract: This application note describes how sampling clock jitter (time interval error or "TIE jitter") affectsthe performance of delta-sigma digital-to-analog converters (DACs). New insights explain the importanceof separately specifying low-frequency (< 2x passband frequency) and high-frequency or wideband (> 2xpassband frequency) jitter tolerance in these devices. The article also provides an application example ofa simple highly jittered cycle-skipped sampling clock and describes a method for generating a properbroadband jittered clock. The document then goes on to compare Maxim's audio DAC jitter tolerance tocompetitor audio DACs. Maxim's exceptionally high jitter tolerance allows very simple and low-cost sampleclock implementations.
標(biāo)簽： DAC 音頻 數(shù)模轉(zhuǎn)換器 抖動(dòng)
上傳時(shí)間： 2013-10-25
上傳用戶：banyou
The MAX17600–MAX17605 devices are high-speedMOSFET drivers capable of sinking /sourcing 4A peakcurrents. The devices have various inverting and noninvertingpart options that provide greater flexibility incontrolling the MOSFET. The devices have internal logiccircuitry that prevents shoot-through during output-statchanges. The logic inputs are protected against voltagespikes up to +14V, regardless of VDD voltage. Propagationdelay time is minimized and matched between the dualchannels. The devices have very fast switching time,combined with short propagation delays (12ns typ),making them ideal for high-frequency circuits. Thedevices operate from a +4V to +14V single powersupply and typically consume 1mA of supply current.The MAX17600/MAX17601 have standard TTLinput logic levels, while the MAX17603 /MAX17604/MAX17605 have CMOS-like high-noise margin (HNM)input logic levels. The MAX17600/MAX17603 are dualinverting input drivers, the MAX17601/MAX17604 aredual noninverting input drivers, and the MAX17602 /MAX17605 devices have one noninverting and oneinverting input. These devices are provided with enablepins (ENA, ENB) for better control of driver operation.
標(biāo)簽： 17600 MAX 數(shù)據(jù)資料
上傳時(shí)間： 2013-12-20
上傳用戶：zhangxin
Abstract: This application note presents an overview of the operational characteristics of accurate I²C real-time clocks (RTCs),including the DS3231, DS3231M, and DS3232. It focuses on general application guidelines that facilitate use of device resources forpower management, I²C communication circuit configurations, and I²C characteristics relative to device power-up sequences andinitializations. Additional discussions on decoupling are provided to support developing strategies for mitigating power-supply pushingof device frequency.
標(biāo)簽： I2C 高精度 實(shí)時(shí)時(shí)鐘
上傳時(shí)間： 2013-11-23
上傳用戶：WMC_geophy
Control systems are becoming increasingly dependent on digital processing and so require sensors able to provide direct digital inputs. Sensors based on time measurement, having outputs based on a frequency or phase, have an advantage over conventional analogue sensors in that their outputs can be measured directly in digital systems by pulse counting.
上傳時(shí)間： 2013-10-08
上傳用戶：wuyuying
ANALOG INPUT BANDWIDTH is a measure of the frequencyat which the reconstructed output fundamental drops3 dB below its low frequency value for a full scale input. Thetest is performed with fIN equal to 100 kHz plus integer multiplesof fCLK. The input frequency at which the output is −3dB relative to the low frequency input signal is the full powerbandwidth.APERTURE JITTER is the variation in aperture delay fromsample to sample. Aperture jitter shows up as input noise.APERTURE DELAY See Sampling Delay.BOTTOM OFFSET is the difference between the input voltagethat just causes the output code to transition to the firstcode and the negative reference voltage. Bottom Offset isdefined as EOB = VZT–VRB, where VZT is the first code transitioninput voltage and VRB is the lower reference voltage.Note that this is different from the normal Zero Scale Error.CONVERSION LATENCY See PIPELINE DELAY.CONVERSION TIME is the time required for a completemeasurement by an analog-to-digital converter. Since theConversion Time does not include acquisition time, multiplexerset up time, or other elements of a complete conversioncycle, the conversion time may be less than theThroughput Time.DC COMMON-MODE ERROR is a specification which appliesto ADCs with differential inputs. It is the change in theoutput code that occurs when the analog voltages on the twoinputs are changed by an equal amount. It is usually expressed in LSBs.
標(biāo)簽： Converter Defi ADC 轉(zhuǎn)換器
上傳時(shí)間： 2013-11-12
上傳用戶：pans0ul
高的工作電壓高達(dá)100V N雙N溝道MOSFET同步驅(qū)動(dòng) The D810DCDC is a synchronous step-down switching regulator controller that can directly step-down voltages from up to 100V, making it ideal for telecom and automotive applications. The D810DCDC uses a constant on-time valley current control architecture to deliver very low duty cycles with accurate cycle-by-cycle current limit, without requiring a sense resistor. A precise internal reference provides 0.5% DC accuracy. A high bandwidth (25MHz) error amplifi er provides very fast line and load transient response. Large 1Ω gate drivers allow the D810DCDC to drive multiple MOSFETs for higher current applications. The operating frequency is selected by an external resistor and is compensated for variations in VIN and can also be synchronized to an external clock for switching-noise sensitive applications. Integrated bias control generates gate drive power from the input supply during start-up and when an output shortcircuit occurs, with the addition of a small external SOT23 MOSFET. When in regulation, power is derived from the output for higher effi ciency.
上傳時(shí)間： 2013-10-24
上傳用戶：wd450412225
The LTC®3610 is a high power monolithic synchronousstep-down DC/DC regulator that can deliver up to 12Aof continuous output current from a 4V to 24V (28Vmaximum) input supply. It is a member of a high currentmonolithic regulator family (see Table 1) that featuresintegrated low RDS(ON) N-channel top and bottomMOSFETs. This results in a high effi ciency and highpower density solution with few external components.This regulator family uses a constant on-time valleycurrent mode architecture that is capable of operatingat very low duty cycles at high frequency and with veryfast transient response. All are available in low profi le(0.9mm max) QFN packages.
上傳時(shí)間： 2013-11-07
上傳用戶：moerwang
The MAX9257/MAX9258 programmable serializer/deserializer (SerDes) devices transfer both video data and control signals over the same twisted-pair cable. However, control data can only be transmitted during the vertical blank time, which is indicated by the control-channel-enabled output (CCEN) signal. The electronic control unit (ECU) firmware designer needs to know how quickly to respond to the CCEN signal before it times out and how to calculate this duration. This application note describes how to calculate the duration of the CCEN for the MAX9257/MAX9258 SerDes chipset. The calculation is based on STO timeout, clock frequency, and UART bit timing. The CCEN duration is programmable and can be closed if not in use.
標(biāo)簽： SerDes MAXX 9257 9258
上傳時(shí)間： 2014-01-24
上傳用戶：xingisme
該系統(tǒng)由單片機(jī)89S52控制模塊，程控寬帶放大模塊，整形模塊，F(xiàn)PGA內(nèi)頻率、相位差測(cè)量模塊等構(gòu)成，采用等精度測(cè)頻法測(cè)出頻率和周期，可測(cè)量有效值為0.01～5V，頻率范圍1Hz～20MHz信號(hào)的頻率、周期信號(hào)，精度高達(dá)10-6。采用計(jì)數(shù)法測(cè)量相位差，該系統(tǒng)可測(cè)量有效值0.5～5V，頻率10Hz～100kHz信號(hào)的相位差，精度為1°。系統(tǒng)功能由按鍵控制，測(cè)量結(jié)果實(shí)時(shí)顯示，人機(jī)界面友好。 Abstract: The system consists of the following functional blocks:89S52microcontroller controlling module,programmable amplifier module,comparator module,frequency and phase difference testing module in the FPGA.The system use the equal accuracy frequency-examining technique it measures frequency and circle of signal which its ranges is from1Hz to20MHz and the amplitude of which its range is from0.01Vrms to5Vrms,precision is up to10-6.Using of count method,the system detects the phase difference of signal,the amplitude of whic its range is from0.5Vrms to5Vrms and the frequency of which its ranges is from10Hz to100kHz,precision is up to1°,The system functions is controlled by certain keys,measurement results are displayed in real-time and it is friendly interface.
標(biāo)簽： 89S52 單片機(jī) 多功能 計(jì)數(shù)器
上傳時(shí)間： 2013-11-04
上傳用戶：CHINA526
以89S52單片機(jī)和EP1C6Q240C8型FPGA為控制核心的多功能計(jì)數(shù)器，是由峰值檢波、A/D轉(zhuǎn)換、程控放大、比較整形、移相網(wǎng)絡(luò)部分組成,可實(shí)現(xiàn)測(cè)量正弦信號(hào)的頻率、周期和相位差的功能。多功能計(jì)數(shù)器采用等精度的測(cè)量方法，可實(shí)現(xiàn)頻率為1Hz～10MHz、幅度為0.01～5Vrms的正弦信號(hào)的精確測(cè)頻，以及頻率為10Hz～100kHz、幅度為0.5～5Vrms的正弦信號(hào)精確測(cè)相。液晶顯示器能夠?qū)崟r(shí)顯示當(dāng)前信號(hào)的頻率、周期和相位差。該多功能計(jì)數(shù)器精度高，界面友好，實(shí)用性強(qiáng)。 Abstract: A multi-function counter，which uses89S52MCU and EP1C6Q240C8FPGA as a control core，consists of peak detector，A/D conversion，program-controlled amplification，compared shaping and phase-shifting network part.The counter measures the frequency，period and phase of sinusoidal signal.With the equal precision method,the multi-function counter achieves the precise frequency measurement of the sinusoidal signal which its frequency is from1Hz to10MHz，its amplitude is from0.01Vrms to5Vrms，as well as the accurate phase measurement of the sinusoidal signal which its frequency is from10Hz to100kHz，its amplitude is from0.5Vrms to5Vrms.The LCD monitor real-time displays the frequency，period and phase difference of current signal.The multi-function counter features high precision，friendly interface，and strong practical.
標(biāo)簽： FPGA 單片機(jī) 多功能 計(jì)數(shù)器
上傳時(shí)間： 2013-11-15
上傳用戶：gy592333
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