針對船舶氣象儀保障維修而設計的船舶氣象儀測試系統，包括信息處理終端、主儀器檢測模塊、傳感器檢測模塊，各個模塊都采用基于AVR單片機的嵌入式系統，模塊之間通過CAN總線進行通信。結果表明，船舶氣象儀測試系統能夠快速檢測船舶氣象儀故障，與單純依靠人工方式排查故障相比，故障檢測時間縮短了60%以上。 Abstract: The test system of ship meteorological instrument was developed to satisfy the maintenance of ship meteorological instruments，which composed of information processing terminal， testing module of main instrument and testing module of sensors. Each of these modules included an embedded system based on microcontroller of AVR series and communicated with other module by CAN bus. The results show that the test system can judge the fault of ship meteorological instrument quickly and shorten the fault detection time as much as 60% compared with simple manual troubleshooting.
上傳時間： 2013-11-23
上傳用戶：stvnash
本文介紹了基于AT89C52 單片機的自動水溫控制系統的設計及實現過程。該系統具有實時顯示、溫度測量、溫度設定并能根據設定值對環境溫度進行調節實現控溫的目的以及達到上下限溫度報警功能，控制算法是基于數字PID 算法。關鍵詞 ：PID AT89C52 脈寬調制 實時 Abstract ： This article describes AT89C52 single-chip microcomputer-basedautomatic water temperature control system design and implementation process. Thesystem has real-time display, temperature measurement, temperature settings and theenvironment in accordance with the temperature settings adjusted to achieve thepurpose of temperature control and reach the upper and lower limits of temperaturealarm function, the control algorithm is based on the digital PID algorithm.Keyword: PID AT89C52 PWM real time
上傳時間： 2013-10-10
上傳用戶：歸海惜雪
NXP Semiconductor designed the LPC2400 microcontrollers around a 16-bit/32-bitARM7TDMI-S CPU core with real-time debug interfaces that include both JTAG andembedded Trace. The LPC2400 microcontrollers have 512 kB of on-chip high-speedFlash memory. This Flash memory includes a special 128-bit wide memory interface andaccelerator architecture that enables the CPU to execute sequential instructions fromFlash memory at the maximum 72 MHz system clock rate. This feature is available onlyon the LPC2000 ARM Microcontroller family of products. The LPC2400 can execute both32-bit ARM and 16-bit Thumb instructions. Support for the two Instruction Sets meansEngineers can choose to optimize their application for either performance or code size atthe sub-routine level. When the core executes instructions in Thumb state it can reducecode size by more than 30 % with only a small loss in performance while executinginstructions in ARM state maximizes core performance.
上傳時間： 2013-11-15
上傳用戶：zouxinwang
HT47R20A-1時基(Time Base)使用介紹 HT47 系列單片機的時基可提供一個周期性超時時間周期以產生規則性的內部中斷。時基的時鐘來源可由掩膜選擇設定為WDT 時鐘、RTC 時鐘或指令時鐘（系統時鐘/4）；其超時時間范圍可由掩膜選擇設定為“時鐘來源”/212~“時鐘來源”/215。如果時基發生超時現象，則其對應的中斷請求標志（TBF）會被置位，如果中斷允許，則產生一個中斷服務到08H 的地址。
上傳時間： 2013-11-15
上傳用戶：13925096126
Virtex-5, Spartan-DSP FPGAs Application Note This application note demonstrates how efficient implementations of Digital Up Converters(DUC) and Digital Down Converters (DDC) can be done by leveraging the Xilinx DSP IPportfolio for increased productivity and reduced time to development. Step-by-step instruction is given on how to perform system-level trade off analysis and develop the most efficient FPGA implementation, thus allowing engineers a flexible, low-cost and low-power alternative to ASSP technologies.
標簽： Spartan-DSP Virtex FPGAs Ap
上傳時間： 2013-10-23
上傳用戶：raron1989
FeaturesThe following standard features are provided.• Choice of RTOS scheduling policy1. Pre-emptive:Always runs the highest available task. Tasks of identical priorityshare CPU time (fully pre-emptive with round robin time slicing).2. Cooperative:Context switches only occur if a task blocks, or explicitly callstaskYIELD().• Co-routines (light weight tasks that utilise very little RAM).• Message queues• Semaphores [via macros]• Trace visualisation ability (requires more RAM)• Majority of source code common to all supported development tools• Wide range of ports and examples
上傳時間： 2013-10-13
上傳用戶：13162218709
匯編器在微處理器的驗證和應用中舉足輕重，如何設計通用的匯編器一直是研究的熱點之一。本文提出了一種開放式的匯編器系統設計思想，在匯編語言與機器語言間插入中間代碼CMDL（code mapping description language）語言，打破匯編語言與機器語言的直接映射關系，由此建立起一套描述匯編語言與機器語言的開放式映射體系。基于此開放式映射體系開發了一套匯編器系統，具有較高層次上的通用性和可移植性。【關鍵詞】指令集，CMDL，匯編器，開放式 Design of Retargetable Assembler System Liu Ling Feng Wen Nan Wang Ying Chun Jiang An Ping Ji Li Jiu IME of Peking University, 100871【摘要】An assembler plays a very important role in the field of microprocessor verifications and applications, thus how to build a retargetable assembler system has been a hotspot in this field for long time. This paper presents a new method about the retargetable assembler system design.It provides a kind of language CMDL, code mapping description language. During the process of assembling, assembler languages are firstly translated to CMDL, and then mapped to the machine codes. In an other word, CMDL is inserted between assembler languages and machine codes during the translation procedure. As a medium code, CMDL has a lot of features, such as high extraction, strong descript capabilities. It can describe almost all attributes of assembler languages. By breaking the direct mapping relationship between assembler languages and machine codes, the complexities of machine codes are hided to the users, therefore, the new retargetable assembler system has higher retargetable level by converting the mapping from assembler languages and machine codes to assembler languages and CMDL, and implementationof it becomes easier. Based on the new mapping system structure, a retargetable assemblersystem is developed. It proved the whole system has good retargetability and implantability.【關鍵詞】instruction set, symbol table, assembler, lexical analysis, retargetability
上傳時間： 2013-10-10
上傳用戶：meiguiweishi
The PCA9540B is a 1-of-2 bidirectional translating multiplexer, controlled via the I2C-bus.The SCL/SDA upstream pair fans out to two SCx/SDx downstream pairs, or channels.Only one SCx/SDx channel is selected at a time, determined by the contents of theprogrammable control register.
上傳時間： 2014-12-28
上傳用戶：nshark
The PCA9541 is a 2-to-1 I2C-bus master selector designed for high reliability dual masterI2C-bus applications where system operation is required, even when one master fails orthe controller card is removed for maintenance. The two masters (for example, primaryand back-up) are located on separate I2C-buses that connect to the same downstreamI2C-bus slave devices. I2C-bus commands are sent by either I2C-bus master and are usedto select one master at a time. Either master at any time can gain control of the slavedevices if the other master is disabled or removed from the system. The failed master isisolated from the system and will not affect communication between the on-line masterand the slave devices on the downstream I2C-bus.
上傳時間： 2013-10-09
上傳用戶：3294322651
The PCA9542A is a 1-of-2 bidirectional translating multiplexer, controlled via the I2C-bus.The SCL/SDA upstream pair fans out to two SCx/SDx downstream pairs, or channels.Only one SCx/SDx channel is selected at a time, determined by the contents of theprogrammable control register. Two interrupt inputs, INT0 and INT1, one for each of theSCx/SDx downstream pairs, are provided. One interrupt output, INT, which acts as anAND of the two interrupt inputs, is provided.
上傳時間： 2013-12-07
上傳用戶：europa_lin
